LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 140

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-24
MDPE
BF
ABRT
SSI
SIR
EBPI
IID
SCSI Operating Registers
Master Data Parity Error
This bit is set when the LSI53C875 as a master detects
a data parity error, or a target device signals a parity error
during a data phase. This bit is completely disabled by
the Master Parity Error Enable bit (bit 3 of
(CTEST4)).
Bus Fault
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C875 is
bus master, and is defined as a cycle that ends with a
Bad Address or Target Abort Condition.
Aborted
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the
register.
Single Step Interrupt
If the Single Step Mode bit in the
register is set, this bit is set and an interrupt is generated
after successful execution of each SCRIPTS instruction.
SCRIPTS Interrupt Instruction Received
This status bit is set whenever an Interrupt instruction is
evaluated as true.
Extended Byte Parity Error Interrupt
(LSI53C875N only)
This bit is set whenever the LSI53C875 detects a parity
error on one of the four additional parity pins on the
LSI53C875N.
Illegal Instruction Detected
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the LSI53C875 is
operating in single step mode or automatically executing
SCSI SCRIPTS.
Any of the following conditions during instruction
execution also set this bit:
The LSI53C875 is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without
a disconnect occurring.
Interrupt Status (ISTAT)
DMA Control (DCNTL)
Chip Test Four
6
5
4
3
2
1
0