LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 56

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.13.5 Stacked Interrupts
2-32
If you are polling the ISTAT instead of using hardware interrupts, then
masking a fatal interrupt makes no difference since the SIP and DIP bits
in the
IRQ/ pin.
Masking an interrupt after IRQ/ is asserted does not cause IRQ/ to be
deasserted.
The LSI53C875 will stack interrupts if they occur one after the other. If
the SIP or DIP bits in the ISTAT register are set (first level), then there
is already at least one pending interrupt, and any future interrupts are
stacked in extra registers behind the
SCSI Interrupt Status One
(second level). When two interrupts have occurred and the two levels of
the stack are full, any further interrupts set additional bits in the extra
registers behind
Status One
interrupts are cleared, all the interrupts that came in afterward move into
the SIST0, SIST1, and DSTAT. After the first interrupt is cleared by
reading the appropriate register, the IRQ/ pin is deasserted for a
minimum of three CLKs; the stacked interrupts move into the
Interrupt Status Zero
DMA Status
Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SIST0, but does not assert the IRQ/ pin. Since no
interrupt is generated, future interrupts move right into the
Status Zero (SIST0)
being stacked behind another interrupt. When another condition occurs
that generates an interrupt, the bit corresponding to the earlier masked
nonfatal interrupt is still set.
A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but will not be stacked. These could be multiple SCSI interrupts
(SIP set), multiple DMA interrupts (DIP set), or multiple SCSI and
multiple DMA interrupts (both SIP and DIP set).
Functional Description
Interrupt Status (ISTAT)
(SIST1), and
(DSTAT); and the IRQ/ pin is asserted once again.
SCSI Interrupt Status Zero
or
(SIST0),
SCSI Interrupt Status One (SIST1)
DMA Status
(SIST1), and
inform the system of interrupts, not the
SCSI Interrupt Status One
SCSI Interrupt Status Zero
(DSTAT). When the first level of
DMA Status (DSTAT)
(SIST0),
SCSI Interrupt
SCSI Interrupt
(SIST1), or
instead of
SCSI
registers
(SIST0),