LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 193

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

STW
Register: 0x50–0x51 (0xD0–0xD1)
SCSI Input Data Latch (SIDL)
Read Only
SIDL
15
x
x
x
x
SCSI Input Data Latch
(SODL), and SODR full bits in the
(SSTAT0)
SCSI FIFO Test Write
Setting this bit places the SCSI core into a test mode in
which the FIFO is easily read or written. While this bit is
set, writes to the least significant byte of the
Data Latch (SODL)
contained in this register to be loaded into the FIFO.
Writing the least significant byte of the
Latch (SODL)
functions are summarized in the table below.
SCSI Input Data Latch
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery. Data
received from the SCSI bus can be read from this
register. Data can be written to the
Latch (SODL)
LSI53C875 by reading this register to allow loopback
testing. When receiving SCSI data, the data flows into
this register and out to the host FIFO. This register differs
from the
Input Data Latch (SIDL)
SCSI Bus Data Lines (SBDL)
what is currently on the SCSI data bus. The power-up
value of this register is indeterminate.
x
Register
SODL0
SODL1
Name
SODL
x
SCSI Bus Data Lines (SBDL)
and
x
register will cause the FIFO to load. These
register and then read back into the
SCSI Status Two (SSTAT2)
x
Operation
Register
Write
Write
Write
SIDL
x
register cause the entire word
(SIDL),
x
contains latched data and the
FIFO Bits
x
always contains exactly
[15:0]
[15:8]
[7:0]
SCSI Output Data Latch
x
SCSI Status Zero
SCSI Output Data
SCSI Output Data
x
register;
Function
are cleared.
SCSI Output
None
FIFO
Load
Load
x
SCSI
x
[15:0]
5-77
0
x
0