LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 155

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x20 (0xA0)
DMA FIFO (DFIFO)
Read/Write
BO[7:0]
7
x
0
Byte Offset Counter
These bits, along with bits [1:0] in the
(CTEST5)
transferred between the SCSI core and the DMA core. It
is used to determine the number of bytes in the DMA
FIFO when an interrupt occurs. These bits are unstable
while data is being transferred between the two cores.
Once the chip has stopped transferring data, these bits
are stable.
The
bytes transferred between the DMA core and the SCSI
core. The
number of bytes transferred across the host bus. The
difference between these two counters represents the
number of bytes remaining in the DMA FIFO.
The following steps determine how many bytes are left in
the DMA FIFO when an error occurs, regardless of the
transfer direction:
If the DMA FIFO size is set to 88 bytes:
1.
2.
DMA FIFO (DFIFO)
Subtract the seven least significant bits of the
Byte Counter (DBC)
the
If the DMA FIFO size is set to 536 bytes (using bit 5
of the
the 10 least significant bits of the
(DBC)
FIFO Byte Offset Counter, which consists of
bits [1:0] in the
and bits [7:0] of the
0
DMA FIFO (DFIFO)
DMA Byte Counter (DBC)
register, indicate the amount of data
Chip Test Five (CTEST5)
register from the 10-bit value of the DMA
0
BO
Chip Test Five (CTEST5)
0
DMA FIFO (DFIFO)
register counts the number of
register from the 7-bit value of
register.
0
register counts the
register), subtract
DMA Byte Counter
Chip Test Five
0
register.
register
DMA
0
0
[7:0]
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