LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 179

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x47 (0xC7)
General Purpose Pin Control (GPCNTL)
Read/Write
This register is used to determine if the pins controlled by the
Purpose (GPREG)
correspond to bits [4:0] in the
the bits are enabled as inputs, an internal pull-up is also enabled.
ME
FE
R
GPIO4_EN[4:2]
GPIO1_EN[1:0]
ME
7
0
FE
6
0
Master Enable
The internal bus master signal is presented on GPIO1 if
this bit is set, regardless of the state of bit 1 (GPIO1_EN).
Fetch Enable
The internal opcode fetch signal is presented on GPIO0
if this bit is set, regardless of the state of bit 0
(GPIO0_EN).
Reserved
GPIO Enable
The General purpose control, corresponding to bits [4:2]
in the
59, and 57. GPIO4 powers up as a general purpose
output, and GPIO[3:2] power-up as general purpose
inputs.
GPIO Enable
These bits power-up set, causing the GPIO1 and GPIO0
pins to become inputs. Clearing these bits causes
GPIO[1:0] to become outputs.
register are inputs or outputs. Bits [4:0] in GPCNTL
General Purpose (GPREG)
R
5
x
General Purpose (GPREG)
4
0
GPIO
1
2
1
register and pins 60,
register. When
1
1
GPIO
General
0
1
[4:2]
[1:0]
5-63
7
6
5