LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 107

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LSI53C875

Manufacturer Part Number
LSI53C875
Description
PCI to Ultra SCSI I/O Processor
Manufacturer
LSI Logic
Datasheet

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Table 4.9
Name
SCLK
SD[15:0]/,
SDP[1:0]/
SCSI SIgnals
LSI53C875,
LSI53C875J:
113, 115, 116,
117, 85, 86,
87, 89, 102,
103, 105, 106,
107, 108, 110,
111, 112, 101
LSI53C875N:
143, 145, 146,
147, 115, 116,
117, 119, 132,
133, 135, 136,
137, 138, 140,
141, 142, 131
LSI53C875JB:
D13, E10,
C13, D11, J9,
L13 K11, J10,
G10, G9, F13,
F11, F10, F9,
E12, E11, F8,
G13
LSI53C875JB
LSI53C875N,
LSI53C875J,
LSI53C875,
Table 4.9
56/73/M6
Pin No.
describes the SCSI Signals group.
Type
I/O
I
Description
SCSI Clock is used to derive all SCSI-related timings.
The speed of this clock is determined by the
application’s requirements. In some applications SCLK
may be sourced internally from the PCI bus clock (CLK).
If SCLK is internally sourced, then the SCLK pin should
be tied LOW.
SCSI Data includes the following data lines and parity
signals: SD[15:0]/ (16-bit SCSI data bus), and SDP[1:0]/
(SCSI data parity bits).
4-15

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