LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 30

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.3.1 Opcode Fetch Burst Capability
2.4 External Memory Interface
2-6
Setting the Burst Opcode Fetch Enable bit in the
register (0x38) causes the LSI53C875 to burst in the first two longwords
of all instruction fetches. If the instruction is a Memory-to-Memory Move,
the third longword is accessed in a separate ownership. If the instruction
is an indirect type, the additional longword is accessed in a subsequent
bus ownership. If the instruction is a Table Indirect Block Move, the chip
uses two accesses to obtain the four longwords required, in two bursts
of two longwords each.
The LSI53C875 supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. The device also supports Flash ROM updates
through the add-in interface and the GPIO4 pin (used to control V
power supply for programming external memory). This interface is
designed for low speed operations such as downloading instruction code
from ROM. It is not intended for dynamic activities such as executing
instructions.
System requirements include the LSI53C875, two or three external 8-bit
address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 k
HC or HCT external components to be used. If in-system Flash ROM
Functional Description
On every Store instruction. The Store instruction may also be used
to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.
On every write to the
On all Transfer Control instructions when the transfer conditions are
met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.
When the Prefetch Flush bit
unit flushes whenever this bit is set. The bit is self-clearing.
Note:
This feature is only useful if prefetching is disabled.
DMA SCRIPTS Pointer
pull-down resistors on the MAD bus require
(DMA Control
(DCNTL), bit 6) is set. The
DMA Mode (DMODE)
(DSP).
PP
, the