LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 114

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Table 4.11
Table 4.12
4.1 MAD Bus Programming
4-22
Name
GPIO2_
MAS2/
Name
TCK
TMS
TDI
TDO
LSI53C875JB
LSI53C875N,
LSI53C875J,
LSI53C875,
External Memory Interface Signals (Cont.)
JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB Only)
68 /87/J8
Pin No.
LSI53C875JB
LSI53C875N,
LSI53C875J,
130/172/A10
142/185/D7
57/75/N6
58/77/J6
Pin No.
Table 4.12
LSI53C875N, and LSI53C875JB.
The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, are also used to program power-up options for
the chip. A particular option is programmed by connecting a 4.7 k
resistor between the appropriate MAD[x] pin and Vss. The pull-down
resistors require that HC or HCT external components are used for the
memory interface.
Signal Descriptions
MAD[7] has no functionality. Do not place a pull-down resistor on
this pin.
Typ
e
I/O
describes the JTAG Signals group for the LSI53C875J,
Type
Description
General Purpose I/O pin. Optionally, this pin is used as a
Memory Address Strobe 2 if an external memory with more than
16 bits of addressing is specified by the pull-down resistors at
power-up and bit 0 in the
is set.
–
–
–
–
Description
Test Clock pin for JTAG boundary scan.
Test Mode Select pin for JTAG boundary scan.
Test Data In pin for JTAG boundary scan.
Test Data Out pin for JTAG boundary scan.
Expansion ROM Base Address
register