LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 122

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-6
TRG
Register: 0x01 (0x81)
SCSI Control One (SCNTL1)
Read/Write
EXC
ADB
SCSI Operating Registers
EXC
7
0
Note:
ADB
6
0
Writing this bit while not connected may cause the loss of
a selection or reselection due to the changing of target or
initiator modes.
Target Mode
This bit determines the default operating mode of the
LSI53C875. The user must manually set the target or
initiator mode. This is done using the SCRIPTS language
(SET TARTET or CLEAR TARGET). When this bit is set, the
chip is a target device by default. When this bit is cleared,
the LSI53C875 is an initiator device by default.
Extra Clock Cycle of Data Setup
When this bit is set, an extra clock period of data setup
is added to each SCSI send data transfer. The extra data
setup time can provide additional system design margin,
though it affects the SCSI transfer rates. Clearing this bit
disables the extra clock cycle of data setup time. Setting
this bit only affects SCSI send operations.
Assert SCSI Data Bus
When this bit is set, the LSI53C875 drives the contents
of the
data bus. When the LSI53C875 is an initiator, the SCSI
I/O signal must be inactive to assert the
Data Latch (SODL)
the LSI53C875 is a target, the SCSI I/O signal must be
active to assert the SODL contents onto the SCSI bus.
The contents of the
register can be asserted at any time, even before the
LSI53C875 is connected to the SCSI bus. Clear this bit
when executing SCSI SCRIPTS. It is normally used only
for diagnostics testing or operation in low level mode.
DHP
SCSI Output Data Latch (SODL)
5
0
CON
4
0
contents onto the SCSI bus. When
SCSI Output Data Latch (SODL)
RST
3
0
AESP
2
0
onto the SCSI
SCSI Output
IARB
1
0
SST
0
0
0
7
6