LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 51

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.11.3
2.5.11.4
2.5.11.5 Achieving Optimal SCSI Send Rates
2.5.12 Ultra SCSI Synchronous Data Transfers
SCSI Control Three (SCNTL3)
SCSI Transfer (SXFER)
example, if SCLK is 80 MHz and the SCF value is set to divide by two,
then the maximum rate at which data can be received is 10 MHz
(80/(2*4) = 10).
The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI core logic.
This divider must be set according to the input clock frequency in the
table.
The TP[2:0] divider bits determine the SCSI synchronous transfer period
when sending synchronous SCSI data in either initiator or target mode.
This value further divides the output from the SCF divider.
To achieve optimal synchronous SCSI send timings, the SCF divisor
value should be set high, to divide the clock as much as possible before
presenting the clock to the TP divider bits in the
register. The TP[2:0] divider value should be as low as possible. For
example, with an 80 MHz clock to achieve a 20 Mbytes/s Ultra SCSI
send rate, the SCF bits can be set to divide by 1 (001) and the TP bits
to divide by 4 (000). To set for a 10 Mbytes/s send rate for Fast SCSI-
2, the SCF bits can be set to divide by 2 (011) and the TP bits set to
divide by 4 (000).
Ultra SCSI is an extension of current Fast SCSI-2 synchronous transfer
specifications. It allows synchronous transfer periods to be negotiated
down as low as 50 ns, which is half the 100 ns period allowed under Fast
SCSI-2. This will allow a maximum transfer rate of 40 Mbytes/s on a
16-bit SCSI bus. The LSI53C875 requires an 80 MHz SCSI clock input
to perform Ultra SCSI transfers. In addition, the following bit values affect
the chip’s ability to support Ultra SCSI synchronous transfer rates:
PCI Cache Mode
Clock Conversion Factor bits,
bits [2:0] and Synchronous Clock Conversion Factor bits,
Control Three (SCNTL3)
Register, Bits [7:5] (TP[2:0])
Register, Bits [2:0] (CCF[2:0])
register bits [6:4]. These fields now support
SCSI Control Three (SCNTL3)
SCSI Transfer (SXFER)
SCSI
register
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