LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 37

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Table 2.2
BIt Name
Assert SATN/ on Parity
Errors
Enable Parity Checking
Assert Even SCSI Parity
Disable Halt on SATN/
or a Parity Error (Target
Mode Only)
Enable Parity Error
Interrupt
Parity Error
Status of SCSI Parity
Signal
SCSI SDP1 Signal
Latched SCSI Parity
Master Parity Error
Enable
Bits Used for Parity Control and Generation
slave write operations causes a fatal DMA interrupt; SCRIPTS stops
running. Mask this interrupt with the EBPE Interrupt Enable bit, bit 1 in
the
no way affect the generation or checking of the PCI specified parity line.
PCI Cache Mode
DMA Interrupt Enable (DIEN)
Location
SCSI Control
Zero
Bit 1
SCSI Control
Zero
Bit 3
SCSI Control
One
Bit 2
SCSI Control
One
Bit 5
SCSI Interrupt
Enable Zero
(SIEN0), Bit 0
SCSI Interrupt
Status Zero
(SIST0), Bit 0
SCSI Status Zero
(SSTAT0), Bit 0
SCSI Status Two
(SSTAT2), Bit 0
SCSI Status Two
(SSTAT2), Bit 3
and
One
Bit 3
Chip Test Four
(CTEST4), Bit 3
SCSI Status
(SCNTL1),
(SCNTL1),
(SSTAT1),
(SCNTL0),
(SCNTL0),
Description
When this bit is set, the LSI53C875 automatically
asserts the SATN/ signal upon detection of a parity
error. SATN/ is only asserted in initiator mode.
Enables the LSI53C875 to check for parity errors. The
LSI53C875 checks for odd parity. This bit also checks
for parity errors on the four additional parity pins on the
LSI53C875N.
Determines the SCSI parity sense generated by the
LSI53C875 to the SCSI bus.
Causes the LSI53C875 not to halt operations when a
parity error is detected in target mode.
Determines whether the LSI53C875 generates an
interrupt when it detects a SCSI parity error.
This status bit is set whenever the LSI53C875 has
detected a parity error on the SCSI bus.
This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.
This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.
These bits reflect the SCSI odd parity signal
corresponding to the data latched into the
Data Latch (SIDL)
Enables parity checking during master data phases.
register. These additional parity pins in
register.
SCSI Input
2-13