LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 158

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-42
Register: 0x22 (0xA2)
Chip Test Five (CTEST5)
Read/Write
ADCK
BBCK
DFS
MASR
DDIR
SCSI Operating Registers
ADCK
7
0
BBCK
6
0
Clock Address Incrementor
Setting this bit increments the address pointer contained
in the
Next Address (DNAD)
the DNAD contents and the current DBC value. This bit
automatically clears itself after incrementing the
Next Address (DNAD)
Clock Byte Counter
Setting this bit decrements the byte count contained in
the 24-bit
decremented based on the DBC contents and the current
DNAD value. This bit automatically clears itself after
decrementing the
DMA FIFO Size
This bit controls the size of the DMA FIFO. When clear,
the DMA FIFO appears as only 88 bytes deep. When set,
the DMA FIFO size increases to 536 bytes. Using an
88-byte FIFO allows software written for other
LSI53C8XX family chips to properly calculate the number
of bytes residing in the chip after a target disconnect. The
default value of this bit is zero.
Master Control for Set or Reset Pulses
This bit controls the operation of bit 3. When this bit is
set, bit 3 asserts the corresponding signals. When this bit
is cleared, bit 3 deasserts the corresponding signals. Do
not change this bit and bit 3 in the same write cycle.
DMA Direction
Setting this bit either asserts or deasserts the internal
DMA Write (DMAWR) direction signal depending on the
current status of the MASR bit in this register. Asserting
DFS
DMA Next Address (DNAD)
5
0
DMA Byte Counter (DBC)
MASR
4
0
DMA Byte Counter (DBC)
register is incremented based on
register.
DDIR
3
0
BL2
2
x
register. The
register. It is
1
x
BO[9:8]
register.
DMA
DMA
0
x
7
6
5
4
3