LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 154

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-38
31
x
x
x
x
x
x
x
FM
WRIE
Registers: 0x1C–0x1F (0x9C–0x9F)
Temporary (TEMP)
Read/Write
TEMP
SCSI Operating Registers
x
x
x
x
x
Fetch Pin Mode
When set, this bit causes the FETCH/ pin to deassert
during indirect and table indirect read operations.
FETCH/ is only active during the opcode portion of an
instruction fetch. This allows the storage of SCRIPTS in
a PROM while data tables are stored in RAM.
If this bit is not set, FETCH/ is asserted for all bus cycles
during instruction fetches.
Write and Invalidate Enable
This bit, when set, causes the issuing of Memory Write
and Invalidate commands on the PCI bus whenever legal.
These conditions are described in detail in
“PCI Functional Description.”
Temporary
This 32-bit register stores the Return instruction address
pointer from the Call instruction. The address pointer
stored in this register is loaded into the
Pointer (DSP)
executed. This address points to the next instruction to
execute. Do not write to this register while the LSI53C875
is executing SCRIPTS.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
x
x
x
TEMP
x
x
x
register when a Return instruction is
x
x
x
x
x
x
x
x
DMA SCRIPTS
x
x
Chapter 3,
x
x
[31:0]
x
0
x
1
0