LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 173

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

When performing consecutive 8-bit reads of the
SCSI Interrupt Status Zero
(SIST1)
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the ISTAT SIP and DIP bits may not
be set, read the
Status One (SIST1)
avoid missing a SCSI interrupt. For more information on interrupts, refer
to
M/A
CMP
SEL
RSL
SGE
Chapter 2, “Functional Description.”
registers (in any order), insert a delay equivalent to 12 CLK
Initiator Mode: Phase Mismatch;
Target Mode: SATN/ Active
In initiator mode, this bit is set if the SCSI phase asserted
by the target does not match the instruction. The phase
is sampled when SREQ/ is asserted by the target. In
target mode, this bit is set when the SATN/ signal is
asserted by the initiator.
Function Complete
This bit is set when an arbitration only or full arbitration
sequence is completed.
Selected
This bit is set when the LSI53C875 is selected by another
SCSI device. The Enable Response to Selection bit must
be set in the
RESPID register must hold the chip’s ID) for the
LSI53C875 to respond to selection attempts.
Reselected
This bit is set when the LSI53C875 is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the
register (and the RESPID register must hold the chip’s
ID) for the LSI53C875 to respond to reselection attempts.
SCSI Gross Error
This bit is set when the LSI53C875 encounters a SCSI
Gross Error Condition. The following conditions can result
in a SCSI Gross Error Condition:
SCSI Interrupt Status Zero (SIST0)
Data Underflow – reading the SCSI FIFO when no
data is present.
registers before the
(SIST0), and
SCSI Chip ID (SCID)
DMA Status (DSTAT)
SCSI Interrupt Status One
DMA Status
SCSI Chip ID (SCID)
register (and the
and
SCSI Interrupt
(DSTAT),
register to
5-57
7
6
5
4
3