LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 151

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x19 (0x99)
Chip Test One (CTEST1)
Read Only
FMT[3:0]
FFL[3:0]
Register: 0x1A (0x9A)
Chip Test Two (CTEST2)
Read/Write
DDIR
DDIR
7
1
7
0
SIGP
1
6
0
FMT[3:0]
Byte Empty in DMA FIFO
These bits identify the bottom bytes in the DMA FIFO that
are empty. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is empty, then
FMT3 is set. Since the FMT flags indicate the status of
bytes at the bottom of the FIFO, if all FMT bits are set,
the DMA FIFO is empty.
Byte Full in DMA FIFO
These status bits identify the top bytes in the DMA FIFO
that are full. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is full then
FFL3 is set. Since the FFL flags indicate the status of
bytes at the top of the FIFO, if all FFL bits are set, the
DMA FIFO is full.
Data Transfer Direction
This status bit indicates which direction data is being
transferred. When this bit is set, the data is transferred
from the SCSI bus to the host bus. When this bit is clear,
the data is transferred from the host bus to the SCSI bus.
CIO
1
5
x
CM
4
1
4
x
SRTCH
3
0
3
0
TEOP
0
2
0
FFL[3:0]
DREQ
0
1
0
DACK
0
0
0
1
[7:4]
[3:0]
5-35
7