LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 12

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LSI53C875

Manufacturer Part Number
LSI53C875
Description
PCI to Ultra SCSI I/O Processor
Manufacturer
LSI Logic
Datasheet

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Tables
xii
2.1
2.2
2.3
2.4
2.5
3.1
3.2
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
5.1
5.2
5.3
5.4
5.5
6.1
6.2
Contents
External Memory Support
Bits Used for Parity Control and Generation
SCSI Parity Control
SCSI Parity Errors and Interrupts
Differential Mode
PCI Bus Commands and Encoding Types
PCI Configuration Register Map
LSI53C875, LSI53C875J, LSI53C875E, and LSI53C875JE
Power and Ground Signals
LSI53C875N Power and Ground Signals
LSI53C875JB and LSI53C875JBE Power and
Ground Signals
System Signals
Address and Data Signals
Interface Control Signals
Arbitration Signals
Error Reporting Signals
SCSI SIgnals
Additional Interface Signals
External Memory Interface Signals
JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB
Only)
Subsystem Data Configuration Table for the LSI53C875E
(PCI Rev ID 0x26)
Subsystem Data Configuration Table for the LSI53C875
(PCI Rev ID 0x04), Revision G Only
External Memory Support
LSI53C875 Register Map
Examples of Synchronous Transfer Periods for SCSI-1
Transfer Rates
Example Transfer Periods for Fast SCSI-2 and Ultra SCSI
Transfer Rates
Maximum Synchronous Offset
SCSI Synchronous Data FIFO Word Count
SCRIPTS Instructions
Read/Write Instructions
2-13
2-14
2-15
2-20
3-12
4-10
4-11
4-12
4-13
4-14
4-15
4-18
4-21
4-22
4-23
4-23
4-24
5-16
5-17
5-18
5-28
6-24
2-7
3-3
4-7
4-7
4-8
5-2
6-2

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