cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 99

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-17.
6.3.1.1.2
The Non-DMA Interrupt Descriptor is 64 bits wide, and the detailed description of its field is provided in
The most significant bit in the Non-DMA Interrupt Descriptor is always read as 1.
Table 6-18.
28500-DSH-002-C
35:33
32:28
27:14
13:1
0
63
62:58
57:48
47:43
42
Bit
Bit
Field Name
Field Name
BLEN[13:0]
EOCE[2:0]
CH [9:0]
RxERR/
CHDIR
ILOST
RSVD
RSVD
RSVD
RSVD
DMA Interrupt Descriptors Format (2 of 2)
Non-DMA Interrupt Descriptors Format (1 of 3)
TYP
Non-DMA Interrupt Descriptor Format
Value
Value
—
—
—
—
—
—
—
—
—
1
When this is an RxEOM interrupt then this field specifies the error type:
0: Receiver error (decoded)—no error.
1: RxBUFF—Overflow.
2: RxCOFA—Change Of Frame Alignment.
3: RxOOF—Out Of Frame.
4: RxABT—Abort Termination. It is generated when the received message is terminated with an abort
sequence (seven consecutive 1s) instead of the specific closing flag, 7Eh.
5: RxLNG—Long Message. Generated when received message length (after zero extraction) is greater
than the selected maximum message size. The message reception is terminated and transfer to shared
memory is not performed.
6: RxALIGN—Byte Alignment Error. It is generated when the message payload size (after zero
extraction), is not a multiple of 8 bits. This generally occurs with an FCS error. The FCS interrupt is not
generated if the ALIGN interrupt was issued.
7: RxFCS—Frame Check Sequence Error. It is generated when received HDLC frame is terminated with a
byte aligned 7Eh flag but the computed FCS does not match the received FCS.
When this is an RxEOCE or TxEOCE interrupt then this field specifies the command type that was
executed:
0: Activate
1: Deactivate
2: Jump
3–7: Reserved
Reserved
Receiver—Number of received bytes.
Transmitter—Buffer length.
Reserved
0: No interrupts have been lost.
1: Interrupt Lost. Generated when internal interrupt queue is full and more interrupt conditions are
detected. Because CX28500 cannot store the newest interrupt descriptors, it discards the new interrupts
and overwrites this bit in the last interrupt in an internal queue prior to that interrupt being transferred
out to shared memory. The integrity of the descriptor being overwritten is maintained completely.
Interrupt Descriptor Type 1.
Reserved.
The channel number causing the interrupt.
Reserved.
0: Receive direction.
1: Transmit direction.
Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Description
Description
Memory Organization
Table
6-18.
84