cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 83

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

A TSBUS frame structure is defined as an integer multiplication of bytes. There are seven signals that define the
TSBUS interface. In the TSBUS mode, the Rx and Tx are synchronous (i.e., the first bit of Tx and Rx frame is
sampled on the falling edge or rising edge of RCLK/TCLK on TDAT/RDAT). TSTB defines the frame
synchronization, which marks the first bit of Rx/Tx frame. TSTUFF acts as a flow control signal that indicates “stuff”
(update) to be sent on the following time slot mapped to the logical channel. TSTUFF is sampled in the first two bits
of the channel’s time slot.
In the TSBUS transmit direction, CX28500 requires the stuff status for each time slot to be presented at its
TSTUFF input exactly eight time slots in advance of the actual time slot for which the stuff status is applied. The
amount of the TSTUFF advance is fixed at eight time slots even though the number of time slots within a frame
might vary.
For the receive direction, CX28500 requires the stuff status for each time slot to be presented at its RSTUFF input
on the current time slot for which the stuff is applied.
5.2.8
Examples of the payload TSBUS operates at a data rate of 51.84 Mbps. It carries the data path signals derived
from either SONET, SDH, electrical DS3, or the electrical E3 signals.
The data on the Payload TSBUS is framed and consists of 84 time slots.
5.2.8.0.1
Payload Data Paths are as follows:
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28500-DSH-002-C
SONET/SDH Payload
Electrical DS3 to DS1—x28 DS1 672 time slots
Electrical E3 to E1—x16 E1 Framers 651 time slots
STS-1 to DS3/E3 to X28 DS1 (672 time slots) / X21 E1 (651 time slots)
x28 DS1—672 time slots
x21 E1—651 time slots
x16 E1—496 time slots
VT1.5—672 time slots
VT2.0—651 time slots
VT1.5 to DS1—672 time slots
VT2.0 to E1—21 time slots
TUG-2 to DS1—672 time slots
TUG-2 to E1—651 time slots
DS1 F-bits—1 time slot
E1 Si bits—1 time slot
NOTE:
NOTE:
Payload TSBUS
Time Slot Bus Features
F-bits not mapped with DS1 signals.
Time Slot 0 not mapped.
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