cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 62

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 3-3.
28500-DSH-002-C
GENERAL NOTE:
1. An active low signal is detected by a trailing asterisk (*).
Field
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Register 1, Address 04h (2 of 2)
Command
Name
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Type
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
Unused.
Fast back-to-back enable. This bit controls whether or not CX28500, while acting as
master, can perform fast back-to-back transactions to different devices. The
configuration software routine sets this bit if all bus agents in the system are fast back-
to-back capable.
Note that this bit would be presumably set by the system configuration routine after
ensuring that all targets on the same bus had the Fast Back-to-Back Capable Bit set. If
the target is unable to provide the fast back-to-back capability, the target does not
implement this bit and it is automatically retuned as zero when Status register is read.
SERR enable.
Wait cycle control. CX28500 does not support address stepping.
Parity error response. This bit controls CX28500’s response to parity errors.
VGA palette snoop. Unused.
Memory write and invalidate. The only write cycle type CX28500 generates is memory
write.
Special cycles. Unused. CX28500 ignores all special cycles.
Bus master.
Memory space. Access control.
I/O space accesses. CX28500 does not contain any I/O space registers.
If 1, CX28500 takes normal action when a parity error is detected on a cycle as
If 1, CX28500 can generate fast back-to-back transactions to different agents.
If 0, CX28500 can generate fast back-to-back transactions to the same agent.
If 1, disables CX28500’s SERR* driver.
If 0, enables CX28500’s SERR* driver and allows reporting of address parity
If 0, CX28500 ignores parity errors.
If 1, CX28500 is permitted to act as bus master.
If 0, CX28500 is disabled from generating PCI accesses.
If 1, enables CX28500 to respond to memory space access cycles.
If 0, disables CX28500’s response.
errors.
the target.
®
Description
Host Interface
47