cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 137

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

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Notice that the order of configurations follows their internal addresses in CX28500. This enables the Host to
configure all of them using a single write command (CONFIG_WR) after setting the appropriate values in
contiguous locations in its memory. For details see the
Channel operations service request commands are:
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7.1.2.6
This section depicts a typical initialization procedure.
1. PCI Configuration
2. PCI Reset or Soft Chip Reset (a Soft Chip Reset is performed by a direct write to the CX28500 register map—
3. Allocate areas in the share memory for:
4. Initialize values in allocated space for: XXXXXX
5. Loop and wait for the Service Request Length register to be ready. This step confirms that the CX28500
6. Initialize the Interrupt Queue Pointer register and Interrupt Length register by performing a direct write to the
7. Check the port alive availability (i.e., TxPortAlive and RxPortAlive) register by performing direct reads. For each
28500-DSH-002-C
Table 6-28, RSIU Port Configuration Register
writing to TSIU/RSIU Port Configuration register).
Table 6-29, Maximum Message Length Register
Table 6-31, TSLP Channel Configuration Register
Table 6-32, TDMA Buffer Allocation Register
Table 6-33, TDMA Channel Configuration Register
Table 6-34, TSIU Time Slot Configuration Descriptor
Table 6-35, TSIU Time Slot Pointers Register
Table 6-36, TSIU Port Configuration Register
writing to TSIU/RSIU Port Configuration register).
CH_ACT: Channel Activate
CH_DEACT: Channel De-Activate
CH_JMP: Channel Jump
in the Soft Chip Reset register)
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completed its internal initialization.
a. Read the SRQ_LEN through the PCI slave access and check if it is 0.
b. If true, go to the next step.
c. Otherwise continue to check.
CX28500 registers with the address of the Interrupt Queue located in the shared memory and respectively its
length.
active port the correspondent bit in TxPortAlive and RxPortAlive registers needs to be set to 1.
Interrupt Queue
Service Request Table
CX28500 configuration registers (global and local per channel/port/TS basis)
NOTE:
Typical Initialization Procedure
After performing a Soft Chip Reset, it is not necessary to reconfigure the PCI.
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(the Tx PortAlive register needs to be read and verified before
(the Rx PortAlive register needs to be read and verified before
Section
6.2.1.
®
Functional Description
122