cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 188

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

A.13
For each device configuration, there are three sets of standard variables and two sets of statistics. One of the
statistics sets includes a calculation of spare time which takes into account the Host using the Maximum Tolerable
Delay, and afterwards allowing CX28500 to take the remaining bus time to achieve 100% utilization. The second
statistics set does not include spare time and indicates average utilization.
Below, as in the full breakdown of figures, the explanation is in 5 sections:
1. Configuration–configurable variables;
2. Suggested–configurable variables that have suggested values;
3. Calculated–calculated variables common to both statistics sets;
4. Including Spare Time–calculations include Host /others usage of spare time;
5. Not Including Spare Time–calculations not including usage of spare time.
Table A-1.
Table A-2.
Table A-3.
28500-DSH-002-C
Number of Ch
Mem Available (Kb)
Packet Length (Bits)
Ext. Ch Rate (Kbps)
PCI Freq. (MHz)
Read Latency
Write Latency
PCI Bit Mode
Buffer Len (Bits)
Rx Threshold
Tx Threshold
Int. Ch Rate (Kbps)—RX
Int. Ch Rate (Kbps)—TX
PCI Freq (kHz)
Variable Name
Variable Name
Variable Name
Configuration
Suggestions
Calculated (1 of 2)
Summary and Explanation of Terms Used in Calculations
Size of buffer available to each channel in each direction Total of 32 bytes apportioned equally across Number of
FIFO Threshold of TX channels
Actual rate at which the internal SLP buffer fills taking
into account HDLC framing and status bits.
Actual rate at which the internal SLP buffer empties
taking into account HDLC framing.
Frequency of the PCI in kHz.
Number of active channels
Memory available (KB) for all channels
Length of packets, receive and transmit
Channel rate of serial lines (pure) without taking into account the HDLC overhead
PCI clock frequency in MHz
Latency incurred by the PCI due to a read transaction
Latency incurred by the PCI due to a write transaction
Number of bits transferred in one PCI cycle
FIFO Threshold of RX channels
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Description
Description
CX28500 PCI Bus Latency and Utilization Analysis
Description
®
Channels
Set as half the buffer size
Set as half the buffer size
From actual channels rate, packet length and HDLC
overhead.
From actual channels rate, packet length and HDLC
overhead.
From configured PCI frequency.
Calculated
Calculated
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Calculated
173