cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 31

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

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1.8
CX28500 supports 32 fully independent serial ports that can be configured to run in channelized, unchannelized,
T1 or TSBUS mode.
For example, in the channelized mode, the first six ports can operate at 51.84 Mbps (STS-1 rate) while another 22
ports can operate at 8.192 Mbps (4xE1 rate). Four more ports will be unused. Each STS-1 frame transports 28xT1,
1xT3, 21xE1 or mixed T1/E1 VTG paths. The configuration is valid as long as the overall number of time slots per
the whole device is 4096 time slots or less. For other restrictions see
Alternatively, any of CX28500’s ports can interface unchannelized data streams (HDLC or unformatted). In this
mode, each of the first six ports can be configured to operate up to 52 Mbps and any of the remaining 26 ports up
to 13 Mbps. The restriction is that the overall bandwidth must not exceed 390 Mbps (per direction) while operating
at 66 MHz PCI clock cycles or 250 Mbps (per direction) while operating at 33 MHz PCI clock cycles.
CX28500 manages buffer memory for each of the active data channels with common table processing structures.
The on-device features allow data transmission between buffer memory and the serial interfaces with minimum
Host processor intervention. This allows the Host processor to concentrate on managing the higher layers of the
protocol stack.
Figure 1-7
28500-DSH-002-C
Clear to Send (CTS) per-channel control of data transmission
Direct PCI bus interface is supported
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EBUS—Expansion Bus Interface is provided
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TSBUS interface
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580-pin BGA package is used
3.3 V/2.5 V supply; 5 V-tolerant inputs
JTAG access is provided
Low power CMOS technology is used
PCI Bus Interface (rev. 2.1)
32/64-bit multiplexed Address/Data bus minimizes pincount
33/66 MHz operation
Burst DMA capability (i.e., up to 32 dwords) minimizes the bus occupancy
32-bit multiplexed Address/Data
Allows Host to control other local devices
Facilitates Host access to any local memory
Variable bandwidth time slot
Multiple asynchronous paths over single port
Allows SONET/SDH/PDH paths connection
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illustrates CX28500’s system overview.
Mixed VT1.5/VT2 paths
Mixed TU-11/TU-12 paths
Mixed T1/E1 paths
System Overview
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Section
1.2.
Introduction
16