cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 213

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

The Time Slot bus exchanges data over two I/O chip boundaries so care must be taken in ensuring that the data is
exchanged on the right phase of the master TSBUS clock TSB_CLK. A possible solution for ensuring correct data
exchange is for the Slave (CX28500) to transmit data on the Rising edge of TSB_CLK, and sample the Received
data on the falling edge of TSB_CLK.
There is only one Time Slot Frame strobe used (TSB_STB) for transmit and receive direction. There is also only
one clock (TSB_CLK) used in the definition of bit boundaries for transmit and receive. This results in the Time Slot
Frame alignment of the receive and transmit payload (illustrated in
consists of eight serial data bits. The MSB bit for each Time Slot is transmitted first.
E.2.2
The Master generates clock, Frame sync Strobe signal, and Stuff signal. CX28500 will generate Transmit data
(TSB_TDAT) or generate an all-1s Stuff pattern eight time slots after receiving an active Stuff signal
(TSB_TSTUFF). The Master will generate a Frame sync Strobe (TSB_STB) output synchronously with the rising
edge of TSB_CLK.
Transmit Stuff signal (TSB_TSTUFF). The timing values are illustrated in
Interface Timing and Switching Characteristics.
Figure E-3.
28500-DSH-002-C
TSB_TDAT
TSB_CLK
Payload Time Slot Bus Transmit Data (TSB_TDAT)
Transmit Timing
Figure E-3
Transmit Bit n
illustrates the timing requirements for the Transmit.
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T
pwh
T
per
T
pwl
Transmit Bit n+1
T
s
T
h
Figure
®
Table
E-3). Each time slot in the Time Slot Bus
E-4, but see
Transmit Bit n+2
Figure E-4
Section 10.2.5
illustrates the
500052_033
TSBUS
Serial
198