cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 69

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

If an EBUS Write command is enabled, CX28500 transfers—via a PCI burst read—the data from the Host memory
into an internal buffer. The data is transferred over the EBUS in a series of write transactions. The EBE[3:0]* drives
the programmed value EBUS Byte Enabled (EBE) value set in the Access Control Field dword. If EBE[3:0]* is
different from 0000, the Host must insert the valid bytes into the appropriate location.
4.1.2
The ECLK, Expansion Bus Clock, can be configured to operate at the PCI bus rate of either 33 MHz or 66 MHz, or
at half of the PCI bus rate of 33/2 MHz and 66/2 MHz, respectively. This option is selectable by setting the value of
ECLKDIV bit field in EBUS Configuration register. The signal is output on the ECLK signal line. Whether or not a
device on the EBUS requires a synchronous interface, the ECLK signal is available all the time the PCI clock is
available (PCLK). The EBUS clock output can be disabled by appropriately setting the ECKEN bit field in EBUS
Configuration register. If ECLK is disabled, the ECLK output is three-stated.
After PCI reset, the ECLK output pin is three-stated and the ECKEN field in EBUS Configuration register is cleared.
4.1.3
Unlike Conexant’s other HDLC controllers (CX28478/CX28474/CX28472), CX28500 is not connected to the EINT*
pin of the EBUS. The EBUS interrupt line should be connected to PCI interrupt INTB* directly, if it is needed.
4.1.4
CX28500 is able to extend the duration that the address bits are valid for any given EBUS address phase. This is
accomplished by specifying a value between 0 and 7 in the ALAPSE bit field in EBUS Configuration register. The
value specifies the additional ECLK periods the address bits remain asserted. That is, a value of 0 specifies the
address remains asserted for one ECLK period, and a value of 7 specifies the address remains asserted for 8
ECLK periods. Disabling the ECLK signal output does not affect the delay mechanism.
Both pre- and post-address cycles are always present during the address phase of an EBUS cycle. The pre-
address cycle is one ECLK period long and provides CX28500 time to transition between the address phase and
the following data phase. The pre- and post-cycles are not included in the Address Duration.
4.1.5
CX28500 is able to extend the duration that the data bits are valid for any given EBUS data phase. This is
accomplished by specifying a value between 0 and 15 in the ELAPSE bit field in EBUS Configuration register. The
value specifies the additional ECLK periods the data bits remain asserted. That is, a value of 0 specifies the data
remains asserted for one ECLK period, and a value of 15 specifies the data remains asserted for 16 ECLK periods.
Disabling the ECLK signal output does not affect the delay mechanism.
A pre-data and post-data cycle is always present during the data phase of an EBUS cycle. The pre-data cycle is
one ECLK period long and provides CX28500 sufficient setup and hold time for the data signals. The post-data
cycle is one ECLK period long and provides CX28500 sufficient time to transition between the data phase and the
following bus cycle termination. The pre- and post-cycles are not included in the Data Duration.
4.1.6
CX28500 can be configured to wait a specified amount of time after it releases the EBUS and before it requests the
EBUS a subsequent time. This is accomplished by specifying a value between 0 and 15 in the BLAPSE bit field in
EBUS configuration register. The value specifies the additional ECLK periods CX28500 waits immediately after
28500-DSH-002-C
Clock
Interrupt
Address Duration
Data Duration
Bus Access Interval
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Expansion Bus (EBUS)
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