cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 60

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 3-1.
All writable bits in the configuration space are reset to 0 by the hardware reset, PRST* asserted. After reset,
CX28500 is disabled and only responds to PCI configuration write and PCI configuration read cycles. Write cycles
to reserved bits and registers have no effect. Read cycles to reserved bits always result in 0 being read.
3.2
3.2.1
CX28500 is a single function PCI device that provides the necessary configuration space for a PCI bus controller to
query and configure CX28500’s PCI interface. PCI configuration space consists of a device-independent header
region (64 bytes) and a device-dependent header region (192 bytes). CX28500 provides the device-independent
header section only. Access to the device-dependent header region results in 0s being read, and no effect on
writes.
Three types of registers are available in CX28500:
1. Read-Only (RO)—Return a fixed bit pattern if the register is used or a 0 if the register is unused or reserved.
2. Read-Resettable (RR)—Can be reset to 0 by writing a 1 to the register.
3. Read/Write (RW)—Retain the value last written to it.
Sixteen dword registers make up CX28500’s PCI Configuration Space.
of these registers.
3.2.1.1
Table 3-2.
3.2.1.2
The Status register records status information for PCI bus related events. The Command register provides coarse
control to generate and respond to PCI commands.
28500-DSH-002-C
Register
Number
Bit Field
—
14
15
5
31:16
15:0
PCI Configuration Space
Register 0, Address 00h
Byte Offset (hex)
PCI Configuration Registers
PCI Master and Slave
Register 0, Address 00h
Register 1, Address 04h
Device Id
Vendor Id
14h
38h
3Ch
—
Name
31
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Max Latency
8500h—64 channels
8501h—384 channels
8502h—676 channels
8503h—1024 channels
14F1h
24
Min Grant
Reset
Value
16
®
Reserved
Tables 3-2
—
—
Interrupt Pin
through
8
3-8
specify the contents
Host Interface
Interrupt Line
Type
RO
RO
0
45