cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 96

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-14.
Table 6-15.
Table 6-16.
6.3.1.1
The interrupt descriptor describes the format of data transferred into the queue. There are two different types of
interrupt descriptor. The first type represents DMA's block-related interrupts, and the second type represents other
interrupts. Both types are 64-bit fields. Generically, the interrupt descriptor includes fields for the following:
•
•
•
•
All the interrupts are associated with a channel or direction with the following exceptions:
1. When an OOF or COFA condition is detected on a serial port, only one interrupt is generated for the port until
28500-DSH-002-C
Note(s): Since CX28500 must work with 64-bit alignment, there must be an even number of entries in the buffer.
31:15
31:3
14:0
Bit
2:0
Bit
Identifying the source of interrupt from within the CX28500 channel causing the interrupt (0–1023) and
direction (receive or transmit)
Events assisting the Host in synchronization channel activities
Errors and unexpected conditions resulting in lost data, discontinued message processing, or prevented
successful completion of a service request
Number of bytes transferred to or from shared memory
the condition is cleared and the condition reoccurs.
Field Name
IQPTR [31:3]
Field Name
IQLEN[14:0]
IQPTR [2:0]
in CX28500 Register Map
RSVD
Interrupt Queue Descriptor
Interrupt Queue Pointer
Interrupt Queue Length
Interrupt Descriptors
Byte Offset
000Ch
0010h
Value
Value
—
—
0
0
These 29 bits are appended with 000b to form a 64-bit aligned address. This address points to the first
entry (Quadword) of the Interrupt Queue buffer. The Host can change this field while the chip is
operating. However, this results in flushing all interrupts residing in the internal interrupts FIFO.
Ensures 64-bit alignment.
Reserved.
This 15-bit number specifies the number of interrupt descriptors. The maximum size for an interrupt
queue is 32,768 descriptors. This is a 0-based number. A value of 1 indicates that the queue length is 2
descriptors long, the required minimum.
The Host can change this field while the chip is operating. However, this results in flushing all interrupts
residing in the internal interrupts FIFO. After reset, IQLEN is set to 0. This has the effect of blocking all
the interrupt processing by CX28500.
Similarly, writing a 0 to IQLEN forces CX28500 to stop writing interrupts. This feature can be used to
switch interrupt queues. To switch interrupt queues, first write a 0 to IQLEN. Next, write the base address
of the new interrupt queue into IQPTR in the Interrupt Queue Pointer. Finally, write the new interrupt
queue length into IQLEN.
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Interrupt Queue Pointer
Interrupt Queue Length
®
Description
Description
Field Name
Memory Organization
dwords
1
1
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