cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 30

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

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28500-DSH-002-C
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Variable path primitives are supported.
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Per-channel protocol selection is supported
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Configurable logical channels are supported
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Programmable time slot allocation is supported
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Per-channel DMA buffer management is supported
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Self Service mechanism
Unchannelized mode
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Path Payload
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Higher speed ports
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Path overhead (Performance Monitoring and Provisioning) T1
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Non-FCS mode
16-bit FCS mode
32-bit FCS mode
Transparent mode
Standard DS0
Hyperchannel
Subchannel
Pointer mechanism
32 KB per direction receive and transmit (64 Kb per chip) internal FIFO
Configurable DMA threshold per-channel basis
Programmable FIFO size per-channel basis
Configurable number of buffer descriptors per channel
Flexible buffer descriptor handling
Digital Comm/Termination Equipment (DCE/DTE) interfaces
High Speed Serial Interface (HSSI)
Inter-Process Communication (IPC)
V-Series DTE/DCE Interfaces (V.35)
SDSL Modems and Access Concentrators
T3/E3 Frame Relay
Sub-channeling (N × 8 Kbps) where N is between 1 and 7, the fractional bits in an 8-bit time slot.
DS0 (64 Kbps)
N × 64 Kbps, allows all types of hyperchanneling, channelized, unchannelized, or path payload as long
as the bandwidth does not exceed the respective port’s bandwidth limitation
Unchannelized T3 (44.736 Mbps)
Unchannelized E3 (34.368 Mbps)
HSSI (52 Mbps)
Facilities Data Link (FDL)
Common Channel Signalling (CCS)
T3/E3 Terminal Data Link (TDL)
V.51 and V.52 signalling channels
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Introduction
15