cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 109

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-24.
6.6.4
This register, defined in
registers, one for each channel.
Table 6-25.
28500-DSH-002-C
31:29
28:16
15:13
12:0
31:18
17
16
15
14
GENERAL NOTE:
1. One channel maximum must be 32 KB–8 bytes (i.e., ENDAD = 1FFDh and STARTAD = 000h).
2. ENDAD must be greater than STARTAD (i.e., no rollover).
3. Minimal allocation to any channel ≥ 4 dwords (i.e., ENDAD – STARTAD ≥ 3).
FOOTNOTE:
(1)
(2)
Bit
Bit
RDMA_ENDAD must be an odd address (i.e., LSB must be 1).
RDMA_STARTAD must be an even address (i.e., LSB must be 0).
RDMA_STARTAD[12:0]
RDMA_ENDAD[12:0]
RDMA Buffer Allocation Register
RDMA Channel Configuration Register (1 of 2)
Field Name
Field Name
INHRBSD
RDMA Configuration Register
EOCEIEN
ONRIEN
ERRIEN
RSVD
RSVD
RSVD
Table
(1)
(1)
6-25, controls the per channel RxDMA operational mode. There are 1024 such
(2)
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Value
Value
—
—
0
0
0
0
1
0
1
0
1
0
1
Reserved
Ending address of internal channel data buffer pointing to dword.
Reserved
Starting address of internal channel data buffer
Reserved
End Of Command Execution Interrupt disabled.
End Of Command Execution Interrupt enabled. Interrupt generated when a command
(Activate, Deactivate or Jump) execution was completed.
Inhibit Receive Buffer Status Descriptor disabled. At the end of each Receive Data Buffer,
overwrite Rx Buffer Descriptor with Rx Buffer Status Descriptor.
Inhibit Receive Buffer Status Descriptor enabled. At the end of each Receive Data Buffer,
do not overwrite Rx Buffer Descriptor with Rx Buffer Status Descriptor.
ONR Interrupt disabled.
ONR Interrupt enabled. Interrupt generated when a new buffer descriptor is read from the
Host memory and this buffer is Host-owned and NP bit field is 1.
Error Interrupt disabled.
Error Interrupt enabled. Interrupt generated when End Of Message detected and error
occurred (such as: too-long message, FCS error, and message alignment error or abort
condition).
®
Description
Description
Memory Organization
94