cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 108

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-23.
6.6.3
The Buffer Allocation register configures the internal receive memory.
There is one RDMA Buffer Allocation register for each logical channel (i.e., 1024 channels).
CX28500’s internal Rx memory is a 32-KB dual-port RAM, which can be split into 1024 parts, one part for each
channel. The allocation granularity is two dwords. For each active channel it is required to specify the following:
•
•
•
The Host can issue a Service Request to change the value of this register only when the affected channel is
inactive. Additionally, internal data buffer allocation must conform to the following criteria:
1. Host must set the buffers so there is no overlap between buffers belonging to different channels.
2. Allocated memory segments should not have wraparounds. That is, ending addresses must be greater than
3. The Host cannot allocate all of the FIFO to one channel. The maximal allocation to one channel is (all FIFO) –
Each receive channel must be allocated buffer space before the channel can be activated. Other important
considerations for allocation of internal data buffers include the channel’s data rate and PCI latency tolerance. This
architecture of configured buffer allocation is completely flexible and allows the Host to assign larger FIFO buffers
to channels that operate at higher rates. For applications operating high-speed channels (i.e., hyperchanneling) the
Host can increase the FIFO allocation per channel. PCI latency tolerance equals the maximum length of time a
particular channel can operate normally between PCI bus transactions without reaching an internal overflow or
underflow condition. PCI latency tolerance is primarily dependent on each channel FIFO’s buffer size.
describes the bit fields in the RDMA Buffer Allocation register. There are 1024 RDMA Buffer Allocation registers,
one for each channel.
28500-DSH-002-C
2
1
0
Bit
The starting location of internal data buffer
The ending location of internal buffer
A threshold. This value is triggered when a request from DMA needs to be generated to the internal PCI
arbiter. As soon as the channel’s internal FIFO contains more data bytes than this threshold, a request to the
RDMA to serve this channel is generated, meaning transferring data in the FIFO into shared memory. A
request to serve this channel is also generated, regardless of the value of the threshold, if a complete
message, or an End Of Message (EOM), resides in the channel’s FIFO.
starting addresses.
1 quad dwords.
Field Name
FCSTRANS
RSLP Channel Configuration Register (2 of 2)
BUFFIEN
IDLEIEN
RDMA Buffer Allocation Register
Value
0
1
0
1
0
1
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FCS Transfer Normal. Do not transfer received FCS into shared memory along with data message.
Non-FCS Mode. Transfer received FCS into shared memory along with data message. In a Non-FCS
Mode a SHT message detection is disabled.
Overflow Interrupt disabled.
Overflow Interrupt enabled.
CHABT, CHIC, SHT Interrupt disabled.
CHABT, CHIC, SHT Interrupt enabled. Receive Only. When receiver detects change to abort code,
change to idle code, or too-short message, this bit generates an interrupt to indicate condition.
®
Description
Memory Organization
Table 6.6.3
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