cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 47

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 1-8.
28500-DSH-002-C
/ROOF/CTS[31.0]
SPORT[31:0]
ROOF[31:0]
Pin Label
/STB/
CX28500 Hardware Signal Definitions (4 of 7)
(2)(3)(5)
(2)(4)(5)
(2)(3)(5)
Channelized Clear To Send/
Receiver Out-Of-Frame/
Signal Name
TSBUS Strobe
Mindspeed Proprietary and Confidential
Mindspeed Technologies
I/O
I
If ROOFx, the signal is sampled on the specified active edge of the
corresponding receive clock RCLKx (see ROOF_EDGE bit field in
28, RSIU Port Configuration
When it is asserted high, an Out-Of-Frame (OOF) condition interrupt is
indicated, if OOFIEN bit field is set to 1 in RSIU Port Configuration
Register.
While ROOFx is asserted, the received serial data stream is considered
Out-Of-Frame. If OOFABT bit field is set to 1 in
Configuration
and it remains disabled until ROOFx is deasserted, otherwise, the receive
process is enabled.
Upon ROOFx deassertion, if OOFIEN bit field is set to 1 in RSIU Port
Configuration Register, an interrupt Frame Recovery (FREC) is generated.
The data processing resumes for all affected channels.
This signal can also operate as a general Serial Port Interrupt (SPORT) by
clearing the OOFABT bit field and setting the OOFIEN bit field in RSIU Port
Configuration Register (i.e., OOFABT = 0 and OOFIEN = 1). When the
ROOFx signal transitions from high-to-low (deassertion), a SPORT
interrupt is generated and data stream is not affected. If this signal is
used as a general purpose interrupt, no interrupt is generated until this
signal goes from high to low.
If CTSx, the signal is sampled on the specified active edge of the
corresponding transmit clock, TCLKx. (See CTS_EDGE bit field in
Table 6-28, RSIU Port Configuration
If CTS transitions from high-to-low (is deasserted), then the channel
assigned to the time slot will send continuous idle characters after the
current message has been completely transmitted. The message
transmission data continues when this CTS transitions from low to high
again (is asserted). The response time to CTS is a 32 bit-time, meaning
that a new message might be transmitted if the message starts within the
next 32 bits after CTS was deasserted.
If TSTBx, the signal is sampled twice:
If TSTB transitions from low to high assertion, then it marks the first bit
of time slot 0 within the TSBUS frame.
Since there is a single TSTB for both directions, receive and transmit, the
number of configured time slots (RSIU Time Slot Pointers Assignment
Register and TSIU Time Slot Pointers Register) and the RPORT_TYPE or
TPORT_TYPE value (RSIU Port Configuration Register and TSIU Port
Configuration Register) specifying whether the serial port operates in
channelized or unchannelized mode must be identically configured for
both directions per serial port. Unexpected CX28500 behavior may be
generated if this restriction is violated.
1.
2.
Once by the receive circuitry on the specified edge of the
corresponding receive clock, RCLKx. (See RSTB_EDGE bit field
in
Once by the transmit circuitry on the specified edge of the
corresponding transmit clock, TCLKx. (See TTSTB_EDGE bit
field in
Table 6-28, RSIU Port Configuration
®
Table 6-36, TSIU Port Configuration
Register, the receive process is disabled for the entire port
Register).
Definition
Register.)
Table 6-28, RSIU Port
Register.)
Register.)
Introduction
Table 6-
32