cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 44
cx28500
Manufacturer Part Number
cx28500
Description
Cx28500 Multichannel Synchronous Communications Controller
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28500.pdf
(224 pages)
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Table 1-8.
28500-DSH-002-C
WR* (R/WR*)
EAD[31:0]
Pin Label
EBE[3:0]*
BGACK*
(DS*)
(AS*)
HOLD
(BR*)
HLDA
(BG*)
ECLK
RD*
ALE
CX28500 Hardware Signal Definitions (1 of 7)
(6)
Bus Grant Acknowledge
Address Latch Enable
Expansion Bus Clock
Hold Acknowledge
Address and Data
Signal Name
Expansion Bus
Expansion Bus
(Bus Request)
Hold Request
Byte Enables
Write Strobe
Read Strobe
(Bus Grant)
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s/t/s O EBE* contains byte-enabled information for the EBUS transaction. For
s/t/s O High-to-low transition enables write data from CX28500 into peripheral
s/t/s O High-to-low transition enables read data from peripheral into CX28500.
s/t/s O High-to-low transition indicates that EAD[30:0] bus contains valid
t/s I/O EAD[31:0] is a multiplexed address/data bus.
t/s O
t/s O
t/s O
I/O
I
The EBUS clock can be configured to operate at the PCI clock rate (i.e.,
33 MHz or 66 MHz), or at half of the PCI clock rate (i.e., 33/2 MHz or 66/
2 MHz), in which case the PCI clock is divided by two (see field EC_KDIV
in
details on how these signals are used and controlled by the Host, see
Chapter
device. Rising edge defines write. (In Motorola
high throughout read and held low throughout write. Determines
meaning of DS* strobe.)
Held high throughout write operation. (In Motorola mode, DS*
transitions low for both read and write operations and is held low
throughout the operation.)
address. Remains asserted low through the data phase of the EBUS
access. (In Motorola mode, high-to-low transition indicates EBUS
contains a valid address. Remains asserted for the entire access cycle.)
When asserted, CX28500 requests control of the EBUS.
When asserted, CX28500 has access to the EBUS. It is held asserted
when there are no other masters connected to the bus, or asserted as a
handshake mechanism to control EBUS arbitration. If in Intel mode, then
it should be pulled-down. If in Motorola mode, then it should be pulled-
up.
When asserted, CX28500 acknowledges to the bus arbiter that the bus
grant signal was detected and a bus cycle is sustained by CX28500 until
this signal is deasserted. This is used in Motorola mode only.
Table
6-21).
4.0.
®
Definition
®
mode, R/WR* is held
Introduction
29
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