cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 189

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table A-3.
Table A-4.
28500-DSH-002-C
Time to read BD (average)
Time to read BD (max)
Time to update status
MAXDATA
Max L
Max L
Max L
Max L
Amount Data Filled in L
Amount Data Emptied in L
Spare time (RX/TX)
Spare time (Total)
In spare time amount filled/
emptied
Max total in SLP
ch
pci
ch
pci
Variable Name
Variable Name
(ms) RX
(ms) TX
(ms) RX
(ms) TX
Calculated (2 of 2)
Including Spare Time
pci
RX
pci
TX
Average amount of time required to read a buffer
descriptor.
descriptor.
status.
Maximum amount of data that can be transferred across
the PCI to or from the internal SLP buffer.
Maximum amount of time a channel can endure without
a single data transaction before an overflow occurs.
Maximum amount of time the DMA will take from the
end of spare time until the first data transaction from a
specific channel.
Maximum amount of time a channel can wait without a
single data transaction before its internal SLP buffer is
empty.
Maximum amount of time the DMA will take from the
end of spare time until the first data transaction to that
channel.
Amount of data in bits that is filled into the SLP internal
buffer during the maximum time the DMA takes to
service a specific channel with a data transaction.
Amount of data in bits that is transferred from the SLP
internal buffer during the maximum time the DMA takes
to service a specific channel with a data transaction.
100% PCI bus utilization.
Minimum spare time available after considering both
RX/TX channels.
Self explanatory.
Maximum amount of data in SLP internal buffers at any
one time.
Maximum amount of time required to read a buffer
Number of PCI cycles required to update a packet
Amount of time the (RX/TX) FIFO can endure before
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Description
Description
CX28500 PCI Bus Latency and Utilization Analysis
®
Dependent on PCI bit mode and the value of PCI read
latency.
Dependent on PCI bit mode and the value of PCI read
latency.
Dependent on PCI write latency only.
Calculated (by iteration) taking into account amount
filled in spare time, amount filled in while a channel
waits to be serviced, and the channel’s threshold;
separate for receive and transmit channels.
Calculated from threshold, buffer length, and internal
channel rate.
Calculated (by iteration) taking into account PCI bit
mode, PCI bit rate, MAXDATA, and packet transactions
of all channels.
Calculated from threshold, buffer length, and internal
channel rate.
Calculated (by iteration) taking into account PCI bit
mode, PCI bit rate, MAXDATA, and packet transactions
of all channels.
Calculated from channel rate and L
Calculated from channel rate and L
Calculated from L
Calculated from buffer length, threshold, amount filled
in spare time, and amount filled in L
pci
and L
Calculated
Calculated
ch
—
—
pci
pci
pci
.
.
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