cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 102

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-19.
6.3.1.3
6.3.1.3.1
Interrupt management resources are automatically reset upon the following:
•
•
•
•
CX28500 uses two interrupt queues. One is internal to CX28500 and is controlled exclusively by the DMA block.
The other is the Interrupt Queue in shared memory, which is allocated and administered by the Host, and written to
(filled) by CX28500.
Upon initialization, the data in the status descriptor is reset to all 0s, indicating the first location for next descriptor,
the queue is not full, and no descriptors are currently in the queue. Any existing descriptors in the internal queue
are discarded.
The Host must allocate sufficient shared memory space for the Interrupt Queue. Up to 64 K dwords of queue space
are accessible by CX28500, setting the upper limit for the queue size. CX28500 requires a minimum of two
Quadwords of queue space. This sets the lower limit for the queue size.
The Host must store the pointer to the queue and the length in Quadwords of the queue in CX28500 within the
Interrupt Queue Descriptor registers. Issuing the appropriate Host service to CX28500 can do this. As CX28500
takes in the new values, it automatically resets the controller logic as indicated above. This mechanism can also be
used to switch interrupt queues while CX28500 is in full operation.
6.3.1.3.2
Interrupt conditions are detected in both error and non-error cases. CX28500 makes a determination based on
channel and device configuration whether reporting of the condition is to be masked or whether an Interrupt
28500-DSH-002-C
30:16
15
14:0
Bit
Hardware reset
Soft reset
Write to Interrupt Queue Pointer by a direct PCI write
Write to Interrupt Queue Length by a direct PCI write
WRPTR[14:0]
Field Name
RDPTR[14:0]
INTFULL
Interrupt Status Descriptor
Interrupt Handling
Initialization
Interrupt Descriptor Generation
Host Access
R/W
R
R
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Value
—
—
—
Write Interrupt Pointer. 15-bit Quadword index from start of Interrupt Queue up to
where CX28500 is going to insert the next Interrupt Descriptors. The Host may
read this value to get the location of the last descriptor, which was not served yet,
in the queue. As the queue is circular, care must be taken to ensure roll over at
beginning and end of queue. Only CX28500 updates this value. The WRPTR is a
read only bit field.
0: Interrupt Queue Not Full–shared memory.
1: Interrupt Queue Full–shared memory. The Host writing ANY value to the
ReadPtr clears the INTFULL status bit.
Read Interrupt Pointer. 15-bit Quadword index from start of Interrupt Queue up to
where The Host first unread Interrupt Descriptor resides. The Host may read this
value to get the location of the first descriptor, which was not served yet, in the
queue. As the queue is circular, care must be taken to ensure roll over at beginning
and end of queue. Only The Host updates this value. The ReadPtr is a read/write bit
field. Note: Writing the value of the ReadPtr automatically resets the INTFULL
status bit. Therefore, if the value written into RDPTR is the same value as was read
from this field, it is assumed that the Host did read all the interrupt descriptors.
®
Description
Memory Organization
87