cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 20

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 1-5.
The send and receive data can be formatted in the HDLC messages or left unformatted (transparent mode) over
any combination of bits within a selected time slot. CX28500’s protocol message type is specified on a per-channel
basis.
1.3
1.3.1
An on-device PCI 2.1 compliant controller, known as the Host interface, is provided. Access to CX28500 is
available through PCI read, write, and configuration cycles. The PCI bus interface supports DMA bursts for
extremely high message throughput applications, up to 780 Mbps of the aggregate serial port bandwidth (i.e., 390
Mbps per direction).
1.3.2
The CX28500 provides an on-device 32-bit local expansion bus (EBUS) controller that allows a Host processor to
access peripheral memory space on the EBUS. Physical devices interface directly to CX28500 over the PCI using
the configurable memory mapping features.
Although EBUS utilization is optional, the most notable application for the EBUS is the connection to peripheral
devices (e.g., CX28365, a 12-port T3/E3 framer) local to CX28500’s serial ports.
1.3.3
CX28500 provides a TSBUS interface for variable bandwidth time slots, Virtual Serial Port (VSP). A VSP is defined
as an entity—quantified by clock bus rate divided by number of time slots—which provides multiple asynchronous
paths over a single serial port. A programmable number of VSPs per TSBUS are allowed by using the existing start
and end address time slot pointer mechanism. The pointer mechanism allows CX28500 to allocate any number of
VSPs on a given serial port, providing that the total number of VSPs allocated across all ports does not exceed
4096, the total number of logical channels does not exceed 1024, and the serial port clock speed does not exceed
52 MHz. While operating in TSBUS mode, the minimum number of time slots required is 8 per serial port. The
programmable number of time slots, implemented by the pointer mechanism (i.e., configurable start and end
28500-DSH-002-C
GENERAL NOTE:
FOOTNOTE:
(1)
Half of the OC-12 data rate, including overhead.
4 x 52 + 28 x T1
6 x T3 + 26 x T1
Configuration
6 x 52 + 6 x 13
26 x 8 + 4 x T3
STS-1 data rates (51.84Mbps) are achieved when used in combination with the M29503 over the TSBUS.
Examples of Serial Port Configurations With 66 MHz PCI Clock
Maximum
32 x 4E1
32 x 10
4 x 52
CX28500’s Bus Interfaces
PCI—Peripheral Components Interface
EBUS—Local Expansion Bus
TSBUS—Time Slot Bus
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Total Bandwidth
262.144 Mbps
251.232 Mbps
390 Mbps
208 Mbps
320 Mbps
310 Mbps
387 Mbps
390 Mbps
(1)
®
PCI Clock
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Introduction
5