cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 57

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

3.1
The Host interface in CX28500 is compliant with the PCI Local Bus Specification 2.1. CX28500 provides a PCI
interface specific to 3.3 V and 33/66 MHz operation and supports as master a 32-bit or 64-bit bus with multiplexed
address and data lines, and as a slave, a 32-bit PCI bus.
The Host interface can act as a PCI master and a PCI slave, and contains CX28500’s PCI configuration space and
internal registers. When CX28500 needs to access shared memory, it masters the PCI bus and completes the
memory cycles without external intervention.
3.1.1
Generally, when a system initializes a module containing a PCI device, the configuration manager reads the
configuration space of each PCI device on a PCI bus. Hardware signals select a specific PCI device based on a
bus number, a slot number, and a function number. If a device that is addressed (via signal lines) responds to the
configuration cycle by claiming the bus, then that function’s configuration space is read out from the device during
the cycle. Since any PCI device can be a multifunction device, every supported function’s configuration space
needs to be read from the device. Based on the information read, the configuration manager will assign system
resources to each supported function within the device. Sometimes new information needs to be written into the
function’s configuration space. This is accomplished with a configuration write cycle.
CX28500 is a single function device that has device-resident memory to store the required configuration
information. CX28500 supports Function 0 only.
3.1.2
CX28500 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as
required during device operation. CX28500 supports only dword write transactions.
As a PCI slave, CX28500 responds to the following PCI bus operations:
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28500-DSH-002-C
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple (treated like Memory Read in slave mode)
Memory Read Line (treated like Memory Read in slave mode)
Memory Write and Invalidate (treated like Memory Write)
NOTE:
NOTE:
PCI Interface
PCI Initialization
PCI Bus Operations
The PCI Local Bus Specification (Revision 2.1, June 1, 1995) is an architectural, timing,
electrical, and physical interface standard that provides a mechanism for a device to
interconnect with processor and memory systems over a standard bus.
As a PCI slave, CX28500 does not support bursted read or write PCI transactions.
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Host Interface
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