cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 92

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.2.1.2.2
Table 6-8
Table 6-8.
Table 6-9
Table 6-9.
28500-DSH-002-C
FOOTNOTE:
(1)
(2)
(3)
FOOTNOTE:
(1)
Number
dword 0
dword 1
dword 2
Dword
Number
dword 0
dword 1
dword 2
dword 3
Bits [1:0] must equal 0 for dword alignment.
All reserved bits must be written to zeros for forward compatibility.
Bit 31 must be set to 1 for all transactions.
Bit 31 must be set to 1 for all transactions.
Dword
presents the EBUS Configuration Service Request Descriptor.
describes the ECD fields.
OPCODE
SACKIEN
Reserved
FIFO-BURST
EBUS Byte Enable
Length
Pointer Shared Memory
EBUS Base Address Offset
OPCODE[31:27]
EBUS Configuration Service Request Descriptor
Field Descriptions of ECD
Descriptor Field
EBUS Configuration Descriptor (ECD)
Bit 31
(3)
SACKIEN[26]
(1)
Mindspeed Proprietary and Confidential
Mindspeed Technologies
(bits)
Size
14
31
32
5
1
7
1
4
Reserved [25:19]
Value
—
—
—
—
Shared Memory Pointer[31:2]
6
7
0
1
0
0
1
A read from this field returns all zeros. A write to this field does nothing.
Number of dwords to transfer over EBUS (up to 16 K dwords, in bursts of
EBUS_WR
EBUS_RD
SACK interrupt disabled.
Do increment address by 1 after each EBUS access.
Do not increment EBUS address for this access. This feature allows same
location access (i.e., FIFO read/write).
Determinates which byte lanes carry meaningful data in EBUS
transactions. The BE [0] applies to byte 0 (LSB).
up to 32 dwords per burst). LENGTH = 0 is not allowed.
The address of shared memory EBUS base address, where the
configuration of local devices exists. This pointer is dword-aligned, hence
bits [1:0] must equal to 0.
EBUS base (byte-aligned) address for an EBUS transaction.
SACK interrupt enabled.
Reserved
EBUS Base Address Offset[30:0]
FIFO_BURST[18]
(2)
®
(1)
Description
EBUS Byte Enable
[17:14]
Memory Organization
Length[13:0]
Bit 0
77