cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 167

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 10-4.
Table 10-5.
Figure 10-1. PCI Clock (PCLK) Waveform, 3.3 V Clock
28500-DSH-002-C
FOOTNOTE:
(1)
(2)
(3)
FOOTNOTE:
(1)
(2)
Symbol
Input leakage currents include hi-Z output leakage for all bidirectional buffers with three-state outputs.
Signals without pullup resistors must have 3 mA low output current. Signals requiring pullup must have 6 mA; the latter include
FRAME*, TRDY*, IRDY*, DEVSEL*, STOP*, SERR*, and PERR*.
Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
CX28500 works with any clock frequency between DC and 66 MHz, nominally. The clock frequency may be changed at any time during
operation of the system as long as clock edges remain monotonic, and minimum cycle and high and low times are not violated. The clock
may only be stopped in a low state.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-
peak portion of the clock waveform.
Symbol
C
L
T
idsel
T
V
T
pin
—
high
cyc
low
ptp
PCI Interface DC Specifications (2 of 2)
PCI Clock (PCLK) Waveform Parameters, 3.3 V Clock
Clock Cycle Time
Clock High Time
Clock Low Time
Clock Slew Rate
Peak-to-Peak Voltage
0.3
0.4
IDSEL Pin Capacitance
V
Parameter
0.5
cc
V
cc
Pin Inductance
V
Parameter
(2)
cc
(1)
Mindspeed Proprietary and Confidential
Mindspeed Technologies
0.6
(3)
T
VDD_io
high
0.4 VDD_io
33 MHz
Min
30
11
11
1
T
cyc
Condition
—
—
33 MHz
Infinite
0.2 VDD_io
Max
®
T
—
—
—
Electrical and Mechanical Specification
4
low
Min
—
—
0.4 VDD_io
66 MHz
Min
1.5
15
6
6
(min)
V
ptp
Max
20
66 MHz
8
Max
30
—
—
—
4
500052_059
Units
Units
nH
pF
V/ns
ns
ns
ns
V
152