cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 144

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

8.1.1
CX28500 initiates data transfer to the serial interface only if the following conditions are true:
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If TxENBL bit is set to 0 (transmit port disabled), the serial data output signal is placed in high-impedance three-
state. If TxENBL = 1 (port enabled) and a time slot is disabled, the corresponding time slot’s transmitter output is
either a three-state or all 1s depending on the state of the TRITx bit field in the port’s
Configuration
8.1.2
The receiver processes data from the serial interface only if all of the following conditions are true:
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If any one of the above conditions is not true, the receiver ignores the incoming data stream.
Data transfer consists of CX28500 first seeking the (next) message descriptor from the Message Descriptor in
shared memory for each active channel. The buffer descriptor in each message descriptor, plus the protocol mode
set for the channel, dictates the treatment of the incoming bit stream.
8.2
CX28500 supports three HDLC modes. The modes are assigned on a per-channel and direction basis by setting
the PROTOCOL bit field within the RSLP/TSLP Channel Configuration registers. The HDLC modes are as follows:
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HDLC protocol-specific support in the transmitter includes the following:
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28500-DSH-002-C
TxENBL bit set to 1 in
Transmit channel is mapped to time slots, which are enabled in the port’s
Transmit channel has been activated by a Host service request.
If not in unchannelized mode, then CX28500 waits until the first detection of a sync pulse or strobe to get out of
three-state.
RxENBL bit is set to 1 in the port’s
Receive channel is mapped to time slot(s), that are enabled in the port’s
Receive channel has been activated by a Host via service request.
HDLC_NOCRC: HDLC support, no CRC
HDLC-16CRC: HDLC support, 16-bit CRC
HDLC-32CRC: HDLC support, 32-bit CRC
Generate opening/closing/shared flags
Zero bit insertion after five consecutive 1s are transmitted
Generate pad fill between frames and adjust for zero insertions
Generate 0-, 16- or 32-bit CRC (i.e., FCS)
Generate abort sequences upon FIFO underflow condition or as instructed on a per-message basis by the
ABORT field in the message descriptor
Register.
NOTE:
Transmit
Receive
HDLC Mode
Table 6-36, TSIU Port Configuration
If TxENBL = 1 and the port is configured in any channelized mode (i.e., not unchannelized),
until the first TSYNC/STB pulse is detected, that port outputs either a three-state signal or
all 1s depending on the state of the TRITx bit field.
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Table 6-28, RSIU Port Configuration
Register.
®
Section
Section
Register.
6.6.5.
Table 6-36, TSIU Port
6.7.5.
Basic Operations
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