cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 82

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

When the internal COFA is deasserted, CX28500 generates an Interrupt Descriptor with CREC event encoding if
the interrupt is unmasked.
The receive serial bit stream processing resumes when the COFA condition is declared off. If channels are
configured in HDLC mode, channels resume immediately when the COFA condition is declared off. While in
Transparent mode, channels start operating in the first time slot assigned to the logical channel. Thus, after a
RxCOFA, no channel recovery action is required since the channel recovers automatically.
For each transmitter path, the active channel (regardless of message processing) is immediately deactivated. As a
recovery channel action, Host needs to reactivate the channel upon termination of the COFA condition. COFA
detection is not applicable in unchannelized mode. When a COFA condition occurs, the transmit output is three-
stated.
5.2.3
There is no Out Of Frame (OOF) condition while operating in TSBUS mode. The ROOF signal is used as a TSTB
input pin (for reference see
5.2.4
The serial data stream that CX28500 can manage consists of either packetized data or unpacketized data.
CX28500 supports two types of data-stream modes: HDLC and Transparent.
In Transparent mode, message processing for every channel begins in the time slot marked as the first time slot in
the channel’s structure. Regardless of the channel protocol, the user needs to configure the first time slot for both
receive and transmit directions (see RFIRST_TS and TFIRST-TS bit fields in
Configuration Descriptor
For a channel configured for HDLC mode, either transmit or receive direction, the channel will wait for a
synchronization signal from the internal frame synchronization flywheel before starting processing new messages
after channel activation.
A Frame Synchronization Signal (TSTB) must be provided one time, after that, CX28500 keeps track of
subsequent frame bit location within the flywheel mechanism.
5.2.5
The polling mechanism is the same as in the conventional mode.
5.2.6
While operating in TSBUS mode, there is no CTS signal since the related input pin is defined to be TSTB (for
reference see
5.2.7
The TSBUS is a time slot interface. The digital communication data paths and overhead channels consist of
payload data and overhead data derived from either SONET or SDH data streams, and payload and overhead data
derived from either electrical DS3 or E3 data streams. One of the overhead channels may consist of HDSL
messages generated and received by the Command Status Processor (CSP). The messages are provided by the
local processor that is connected to access and configure local device registers. The TSBUS interface is capable of
full-duplex (bidirectional) transmission of data between one device and the CX28500 device. The interface consists
of two, 1-bit wide serial interfaces: a bidirectional payload TSBUS and bidirectional overhead TSBUS.
28500-DSH-002-C
Figure E-1, CX28500 Time Slot Interface
TSBUS Out Of Frame (OOF)/Frame Recovery (FREC)
TSBUS Frame Alignment
TSBUS Polling
TSBUS Channel Clear To Send
TSBUS Interface
and
Figure E-1, CX28500 Time Slot Interface
Table 6-34, TSIU Time Slot Configuration
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Pins).
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Pins).
Descriptor).
Table 6-26, RSIU Time Slot
Serial Interface
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