cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 115

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

a Receive Buffer Status Descriptor, corresponding to the partially received message, indicates a Long Message
error condition, and an interrupt descriptor is generated toward the Host indicating the same error condition.
Table 6-29.
6.7
Transmit path registers contain the information necessary to configure the transmit direction. This configuration
includes registers that are related to the DMA block, Host interface, registers that control the TSLP line processor,
and TSIU.
6.7.1
The TSLP Channel Status register, defined in
It provides information from the TSLP block regarding the channel state and status. There is one TSLP Channel
status register for each of CX28500’s channels (i.e., 1024 registers).
Table 6-30.
28500-DSH-002-C
31:14
13:0
31:4
3:1
0
GENERAL NOTE:
Bit
Bit
Field Name
MAXFRM[13:0]
TACTIVE
Field Name
RSVD
RSVD
The Host may change the value of Maximum Message Length register only if the channel that uses its value (according to
MAXSEL-bit in the configuration memory) is inactive.
Maximum Message Length Register
TSLP Channel Status Register
RSVD
Transmit Path Registers
TSLP Channel Status Register
Host
R
R
R
Value
—
0
Don’t care
Value
Reserved.
Defines a limit for the maximum number of bytes allowed in a received HDLC message. Valid values
for the register range from 0 to 16 K-1.
The formula to set MAXFRM is
MAXFRM = Max Allowed Message Length (bytes) + FCS (bytes)–1.
where
FCS = 0 for Non-FCS Mode
FCS= 2 byte for HDLC-16 Mode
FCS = 4 byte for HDLC-32 Mode
A Too Long Message interrupt is generated when the number of bytes in the processed message
exceeds Max Allowed Message Length.
Mindspeed Proprietary and Confidential
0
0
1
Mindspeed Technologies
Reserved.
Reserved.
Channel Inactive.
The channel has been deactivated due to either a PCI Reset or Soft Chip Reset, or a Service
Request Channel Deactivation or one of the following transmit errors: TxBUFF, TxCOFA.
Channel Active.
Table
6-30, is a Read Only (RO) register.
®
Description
Description
Memory Organization
100