cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 198

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Figure B-2
back-to-back feature enabled. CX28500 performs as a master while operating at 32-bit address-data, a burst write
of 2 dwords, which are transferred during the first cycle and a burst write of 3 dwords, which are transferred during
the second cycle. Both transaction cycles require 4 PCLK cycles.
Figure B-2.
28500-DSH-002-C
GENERAL NOTE:
1. BEx means Byte Enable, where x is a numerical value between 1 and 8. For example, BE1 means byte one is enabled.
C/BE#[3:0]
C/BE#[7:4]
DEVSEL#
AD[63:32]
FRAME#
illustrates, in a specific configuration, CX28500’s PCI transactions while operating as a master, and fast
AD[31:0]
REQ64#
ACK64#
PAR64
TRDY#
IRDY#
PAR
CLK
PCI Burst Write: Two 32-bit Fast Back-to-Back Transactions to Same Target
Back Transactions
Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-
Bus Cmd
Address
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Data1
BE1
Data2
BE2
Bus Cmd
Address
®
Data1
BE1
Data2
BE2
Data3
BE3
500052_041
183