cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 166

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

10.1.4
Power up sequencing involves the order of powering up the I/O and core supplies and the period of time between
powering up these supplies. When the I/O supply (VDD_io) is powered up first, the output drivers can be in an
indeterminate state until the core supply (VDD_c) is powered up. If the delay in the power sequence is too long
(several ms or more), the unknown state of the output drivers can cause system problems. The recommended
power up sequence is first 5 V (VGG), then 3.3 V (VDD_io), and then 2.5 V (VDD_c).
The I/O supply must be powered up before the core supply. Otherwise, a high current will be drawn until the I/O
supply is powered up. The time from the detection of I/O power to the disabling of output drivers and the time from
the detection of core power to the enabling of output drivers will not exceed 100 ns. Therefore, it is recommended
that the core is powered up more than 100 ns after I/O. If core is powered up during the first 100 ns after I/O power-
up, the device may draw more current until the first 100 ns are elapsed.
10.2
10.2.1
This section defines the timing and switching characteristics of CX28500. The major subsystems include the Host
interface, the expansion bus interface, and the serial interface. The Host interface is Peripheral Component
Interface (PCI) compliant. For other references to PCI, see the PCI Local Bus Specification, Revision 2.1, June 1,
1995. The expansion bus and serial bus interfaces are similar to the Host interface timing characteristics; the
differences and specific characteristics common to either interface are further defined.
10.2.2
Reference the PCI Local Bus Specification, Revision 2.1, June 1, 1995 for information the following:
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Table 10-4.
28500-DSH-002-C
C
Symbol
Indeterminate inputs and metastability
Power requirements, sequencing, decoupling
PCI DC specifications
PCI AC specifications
PCI V/I curves
Maximum AC ratings and device protection
out
VDD_io
C
V
V
V
/C
V
I
oh
clk
ih
il
ol
il
in
/C
io
PCI Interface DC Specifications (1 of 2)
Output, Input, and I/O Pin Capacitance
Power-up Sequencing
Timing and Switching Specifications
Overview
Host Interface (PCI) Timing and Switching Characteristic
Input Leakage Current
Output Low Voltage
PCLK Pin Capacitance
Output High Voltage
Input High Voltage
Input Low Voltage
Supply Voltage
Parameter
Mindspeed Proprietary and Confidential
Mindspeed Technologies
(2)
(1)
0 < V
I
I
out
out
Condition
= –500 µA
= 1500 µA
in
—
—
—
—
—
< VDD_io
®
Electrical and Mechanical Specification
0.5 VDD_io
0.9 VDD_io
Min
–0.5
—
—
—
3
5
0.3 VDD_io
0.1 VDD_io
VGG + 0.3
+/-10
Max
3.6
—
10
12
Units
µA
pF
pF
V
V
V
V
V
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