cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 145

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

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HDLC protocol-specific support in the receiver includes the following:
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The Transmit Buffer Descriptor specifies inter-message bit-level operations. Specifically, when the EOM bit field is
set to 1 within a Message Descriptor by the Host, it signifies that the descriptor represents the last buffer for the
current message being transmitted and the bit fields IC and PADCNT take effect. These bits are described in
Section
Additionally, the NP bit field in both Receive and Transmit Buffer Descriptors selects whether CX28500 polls a
Host-owned message descriptor.
8.2.1
CX28500 is configurable to calculate and insert either a 16- or 32-bit Frame Check Sequence (FCS) for HDLC
packets, provided the packet length contains a minimum of 2 octets. The FCS is always calculated over the entire
packet length.
For all HDLC modes that require FCS calculation, the polynomials used to calculate FCS are according to ITU-T
Q.921 and ISO 3309-1984.
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8.2.2
For HDLC modes only, CX28500 supports the use of opening and closing message flags. The 7Eh (01111110b)
flag is the opening and closing flag. An HDLC message is always bounded by this flag at the beginning and the end
of the message.
CX28500 supports receiving a shared flag where the closing flag of one message can act as the opening of the
next message. CX28500 also supports receiving a shared-zero bit between two flags—that is, the last zero bit of
one flag is used as the first zero bit of the next flag. Receiving a shared zero between the FCS and the closing flag
is not supported.
CX28500 can be configured to transmit a shared flag between successive messages by configuring the bit field
PADCNT in each transmit buffer descriptor. CX28500 does not transmit shared-zero bits between successive flags.
28500-DSH-002-C
Data polarity inversion of all bits (including flags and padfill characters)
Detection and extraction of opening/closing/shared flags
Detection of shared-0 between successive flags
Zero bit extraction after five consecutive 1s are received
Detect changes in pad fill idle codes
Check and extract 0-, 16- or 32-bit FCS
Check frame length
Check for octet alignment. Failures result in EOM and an error code in the buffer/interrupt descriptor
Check for abort sequence reception
After channel activation, check for the first flag character to be received and generate a CHIC interrupt
CRC-16
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CRC-32
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8.2.5.
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Frame Check Sequence
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Opening/Closing Flags
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16
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12
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11
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Mindspeed Proprietary and Confidential
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Mindspeed Technologies
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Basic Operations
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