cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 119
cx28500
Manufacturer Part Number
cx28500
Description
Cx28500 Multichannel Synchronous Communications Controller
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28500.pdf
(224 pages)
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memory location that belongs to the configured port. Time Slot pointer allocation is described in TSIU Time Slot
Pointer Allocation.
The bit fields of TSIU Time Slot Configuration Descriptor include information:
•
•
•
•
Table 6-34.
6.7.6
There is one TSIU Time Slot Pointer Allocation Descriptor for each of CX28500’s 32 serial ports. This register,
defined in
between the configured end and start address specifies the number of time slots allocated for the specified serial
port.
28500-DSH-002-C
31:13
12:3
2
1
0
GENERAL NOTE:
1. The timeslot map registers have no default values and may be active after reset, so they must be configured before activating the port.
Bit
Time slot is enabled or disabled
Time slot is a full DS0, or subchanneling enabled so that only a part of 64 Kbps transports information
Indicates if it is the last time slot assigned to the logical channel
Logical channel number (1024)
Table
TSIU Time Slot Configuration Descriptor
TCHANNEL [9:0]
TMASKEN_SB
Field Name
TTS_ENABLE
6-35, sets the start and end time slot address for the specific configured port. The difference
TLAST_TS
NOTE:
TSIU Time Slot Pointer Assignment Register
RSVD
For polling to work properly and efficiently, it is mandatory that the FIRST (receive time
slot)/LAST (transmit time slot) indications be configured for each channel regardless of the
operational mode (i.e., HDLC, transparent, etc.). The polling mechanism in the CX28500
uses these markings as triggering points. When configured correctly, CX28500 polls on a
channel once at the selected poll throttle rate instead of polling at every time slot allocated
to that channel, as in the case of hyperchannels. When a channel consists of only one time
slot, as in a DS0 channel, its corresponding receive time slot should have the FIRST_TS bit
set. Likewise, its corresponding transmit time slot should have the LAST_TS bit set.
Value
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0
0
1
0
1
0
1
Reserved.
Channel assigned to the time slot.
Time Slot Disabled.
Time Slot Enabled.
Do not use the data mask for this time slot for this channel. This means all 8 bits are
processed. (Subchanneling disabled)
Allow using the data mask for this time slot for this channel. This means only the bits
specified by the data mask are processed. (Subchanneling enabled)
Indicates that this is not the last time slot where this channel appears in this frame.
Indicates that this is the last time slot where this channel appears in the frame.
If a serial port is configured to operate in channelized mode, each channel defined to operate
over the serial port must have one time slot assigned to that logical channel that is defined as
the last time slot for that channel. In unchannelized mode, this bit must be set in the single
time slot assigned.
®
Description
Memory Organization
104
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