cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 112

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

4. If serial port is configured to channelized TSBUS mode, RSIU Time Slot Pointer Allocation Descriptor is
In the case of unchannelized mode (i.e., the RPORT_TYPE field in RSIU Port Configuration register is
programmed to 0), CX28500 assumes that only one entry (the one pointed to by STARTAD) is used for this port.
This frees the ENDAD pointer to point to any location in the RSIU time slot memory. The differences in these
pointers now define the number of time slots to count for polling purposes as described in section Descriptor
Polling.
Table 6-27
Table 6-27.
6.6.7
There is a Receive Port Configuration register for each serial port. It defines how CX28500 interprets and
synchronizes the received bit streams associated with the serial port.
Table 6.6.7
Table 6-28.
28500-DSH-002-C
31:28
27:16
15:12
11:0
31:14
13
12
GENERAL NOTE:
Bit
Bit
configured to support more than eight time slots and the RPORT_TYPE bit field in RSIU Port Configuration
register must be set to channelized TSBUS mode.
describes the bit fields in RSIU Time Slot Pointer Allocation Descriptor.
describes the bit fields in RSIU Port Configuration register.
RSTARTAD_TS[11:0]
RENDAD_TS[11:0]
Writing RXENBL from 0 to 1 forces the port to realign itself to the incoming sync (if channelized) and generate RCOFA. In
unchannelized port mode, the logical channel must be deactivated.
RSIU Time Slot Pointer Allocation Register
RSIU Port Configuration Register (1 of 3)
Field Name
Field Name
RSVD
RSVD
RSIU Port Configuration Register
RXENBL
RSVD
RSVD
(1)
Value
—
—
0
0
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Value
0
0
1
0
Reserved.
Ending location in the Receive Time Slot Map of the last time slot assigned to this port.
Reserved.
Starting location in the Receive Time Slot Map of the first time slot assigned to this port.
Reserved.
Receive Port Disabled. Logically resets the serial port, regardless of RTS_ENABLE bit
field in RSIU Time Slot Configuration Descriptor. This does not affect the bit values in
any time slot descriptor. When the serial port becomes inactive, no data is transferred to
the SLP.
Receive Port Enabled. This bit field acts as a logical AND between RTS_ENABLE bit field
in RSIU Time Slot Configuration Descriptor and time slot.
Logically, if RTS_ENABLE bit field in RSIU Time Slot Configuration Descriptor is enabled,
it allows all channels with time slot enable bits set to start processing data. This does not
affect the bit values in any time slot descriptor.
Reserved.
®
Description
Description
Memory Organization
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