cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 201

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

In
64-bit address-data. A burst write of 4 dwords are transferred during the first cycle and a burst read of 6 dwords are
transferred during the second cycle. It can be observed that the first cycle requires 3 PCLK cycles and the second
cycle requires 6 PCLK cycles.
Figure B-5.
28500-DSH-002-C
Figure
GENERAL NOTE:
1. BEx means Byte Enable, where x is a numerical value between 1 and 8. For example, BE1 means byte one is enabled.
C/BE#[3:0]
C/BE#[7:4]
DEVSEL#
AD[63:32]
B-5, CX28500 performs PCI transactions as a master while fast back-to-back enabled and it operates at
FRAME#
AD[31:0]
REQ64#
ACK64#
PAR64
TRDY#
IRDY#
PAR
CLK
PCI Burst Write Followed by Burst Read: Fast Back-to-Back to Same Target
Bus Cmd
Address
Back Transactions
Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-
Data1
Data2
BE1
BE2
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Data3
Data4
BE3
BE4
Bus Cmd
Address
BE1
BE2
®
Data1
Data2
Data4
Data3
BE3
BE4
Data5
Data6
BE5
BE6
500052_043
186