cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 159

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

8.3.4.2
Reason:
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Effects:
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Channel Level Recovery Actions:
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8.3.5
Receive errors are service-affecting and may require a corrective action by the Host to resume normal processing.
8.3.5.1
Same as HDLC mode.
Reasons:
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Effects:
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Channel Level Recovery Actions:
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28500-DSH-002-C
Signal failure, glitch, or realignment caused by the physical interface sourcing the TSYNC/STB input signal.
Causes serial interface to enter COFA condition until a TSYNC/STB pulse arrives and is followed by at least
one frame for this port, without another unexpected TSYNC/STB pulse.
For every active channel on the respective port, TSLP places channels into the deactivate state, wherein TSLP
sends a repetitive all ones sequence.
Transmit output is three-stated.
Transmit channel complete reactivation is required.
Degradation of Host subsystem performance.
Shortage of shared memory buffers. The receive buffer CX28500 needs to fill is presently Host-owned.
PCI bus congestion.
RxBUFF Interrupt (if BUFFIEN = 1 in
Data received during an overflow condition is discarded.
Data in the internal FIFO is copied to shared memory, the Receive Buffer Status Descriptor is written with
ONR = HOST, EOM = 1, ERROR = BUFF (if INHRBSD = 0 in
If ERRIEN is set in
overflow.
When the overflow condition ends (i.e., space becomes available in the channel FIFO), RSLP automatically
restarts data processing. However, RSLP ignores all time slots until reaching the time slot marked “first.”
RDMA is not affected and continues shared memory buffer processing.
If possible, increase internal FIFO size assigned to this channel. For this action, the channel must first be
deactivated.
If necessary, alleviate PCI bus congestion.
Notice that channel reactivation is not required.
Transmit Change Of Frame Alignment (COFA)
Receive Errors
Receive Overflow [BUFF]
Section 6.6.4
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Section
Section
6.6.2).
6.7.4, an RxERR interrupt is generated, indicating an RxBUFF
Section 6.6.4
®
and
Section
6.7.4).
Basic Operations
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