cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 185

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Hence, max L
or,
Where DATA is the maximum amount, in dwords, that can be transferred from a channel during one PCI
transaction. PCI Mode is the number of bits transferred by the PCI in one clock.
The Maximum Feasible PCI Latency for a given transmit channel (max L
of time in seconds that a transmit channel must wait until its first data transaction. This can be considered as the
amount of time required to service all the receive channels plus the amount of time required to service all but one
of the transmit channels. This involves updating status and reading new buffer descriptors for all channels in both
directions, transferring data to the Host memory for all receive channels, and transferring data from the Host
memory to the SLP internal buffer for all but one of the transmit channels.
Hence max L
or,
Where DATA is the maximum amount, in dwords, that can be transferred from a channel during one PCI
transaction. PCI Mode is the number of bits transferred by the PCI in one clock.
A.9
The Maximum Endurable Latency of a channel (L
the first data transaction.
The timing of the Endurable Latency for a given receive channel (L
DMA service. The interval ends on the clock that the first dword of data is removed from the channel’s SLP buffer
by the DMA for transferal to Host memory, or at worst when its buffer is full.
The timing of the Endurable Latency for a given transmit channel (L
DMA service (i.e., when the FIFO empties to threshold level). The interval ends on the clock that the first dword of
data is moved from Host memory and is transferred to that channel’s SLP buffer by the DMA, or at worst when its
buffer is empty.
L
28500-DSH-002-C
ch-rx
=
----- -
f
1
ch
(BuffLen – Thr
pci-tx
pci-rx
NOTE:
can be represented by the equations:
Maximum Endurable Latency
can be represented by the equations:
------- -
f
rx
pci
1
)
Both of these maximum feasible PCI latency times are internal latencies and do not include
any external influences such as PCI arbitration.
⎧
⎨
⎩
------- -
f
------- -
f
NumCH
pci
------- -
f
pci
1
1
pci
1
∑
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
NumCH
NumCH
NumCH
∑
∑
∑
⎛
⎝
6
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Mindspeed Technologies
+
⎛
⎝
(
2 w
(
2
2 Read BD
2 Read BD
•
•
•
•
⎛
⎝
3
+
+
2
⎛
⎝
•
------------------------ -
PCIMode
⎛
⎝
ch
3
64
) is the amount of time that a specific channel can endure until
+
+
+
⎛
⎝
Write DATA
Read DATA
-------------------------- -
PCI Mode
CX28500 PCI Bus Latency and Utilization Analysis
⎞
⎠
64
+
r
⎞
⎠
+ +
⎞
⎠
2
+
+
+
ch-rx )
r
2 Write STATUS
2 Write STATUS
DATA
®
ch-tx )
⎞
⎠
•
•
+ +
3
starts when that channel first requests
pci-tx
starts when that channel first requests
+ +
DATA
6
) is defined to be the maximum length
3 w
•
+
r
⎞
⎠
⎞
⎠
)
)
+
+
+
+
NumCH 1
NumCH 1
Num CH 1
NumCH 1
∑
∑
∑
∑
–
–
–
–
(
(
3
2
(
(
Write DATA
Read DATA
+
+
DATA
DATA
+
+
r
w
)
)
)
)
⎫
⎬
⎭
⎫
⎬
⎭
⎫
⎬
⎭
⎫
⎬
⎭
170