cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 70

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

releasing the bus. That is, a value of 0 specifies CX28500 will wait for one ECLK period, and a value of 15 specifies
16 ECLK periods. Disabling the ECLK signal output does not affect this wait mechanism.
The bus grant signal (HLDA/BG*) is deasserted by the bus arbiter only after the bus request signal (HOLD/BR*) is
deasserted by CX28500. As the amount of time between bus request deassertion and bus grant deassertion can
vary from system to system, it is possible for a misinterpretation of the old bus grant signal as an approval to
access the EBUS. CX28500 provides the flexibility— through the bus access interval feature—to wait a specific
number of ECLK periods between subsequent bus requests. If the signal (HLDA/BG*) is permanently asserted,
then there is a minimum of 3 ECLK periods between transactions.
Refer to EBUS timing
Write/Read Cycle, Motorola-Style
4.1.7
CX28500 provides a significant improvement in the EBUS interface compared to previous Conexant HDLC
devices. PCI utilization is dramatically improved by enabling the EBUS accesses, reads and writes, to be burst over
the PCI bus—when EBUS is extensively used to access EBUS peripheral during normal operation.
4.1.8
A microprocessor can be added to handle peripheral devices that require additional processing power. The
MPUSEL bit field in EBUS Configuration register specifies the type of microprocessor interface to use for the
EBUS.
If Intel-style protocol is selected, the following signals are effective:
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If Motorola-style protocol, the following signals are effective:
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28500-DSH-002-C
ALE–Address Latch Enable, asserted high by CX28500 to indicate that the address lines contain a valid
address. This signal remains asserted for the duration of the access cycle.
RD*–Read, strobed low by CX28500 to enable data reads out of the device and is held high during writes.
WR*–Write, strobed low by CX28500 to enable data writes into the device and is held high during reads.
HOLD–Hold Request, asserted high by CX28500 when it requests the EBUS from a bus arbiter.
HLDA–Hold Acknowledge, asserted high by bus arbiter in response to HOLD signal assertion. Remains
asserted until after the HOLD signal is deasserted. If the EBUS is connected and there are no bus arbiters on
the EBUS, then this signal must be asserted high at all times.
HLDA is treated as an asynchronous signal.
AS*–Address Strobe, driven low by CX28500 to indicate that the address lines contain a valid address. This
signal remains asserted for the duration of the access cycle.
DS*–Data Strobe, strobed low by CX28500 to enable data reads or data writes for the addressed device.
R/WR*–Read/Write, held high throughout read operation and held low throughout write operation by CX28500.
This signal determines the meaning (read or write) of DS*.
BR*–Bus Request, asserted low by CX28500 when it requests the EBUS from a bus arbiter.
BG*– Hold Acknowledge, asserted low by bus arbiter in response to BR* signal assertion. Remains asserted
until after the BR* signal is deasserted. If the EBUS is connected and there are no bus arbiters on the EBUS,
then this signal must be asserted low at all times.
BGACK*–Bus Grant Acknowledge, asserted low by CX28500 when it detects BGACK* currently deasserted.
As this signal is asserted, CX28500 begins the EBUS access cycle. After the cycle is finished, this signal is
deasserted indicating to the bus arbiter that CX28500 has released the EBUS.
PCI to EBUS Interaction
Microprocessor Interface
diagrams—Figure 10-7, EBUS Write/Read Cycle, Intel-Style
(Motorola).
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Mindspeed Technologies
®
(Intel) and
Expansion Bus (EBUS)
Figure 10-8, EBUS
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