cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 3

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

CX28500
Multichannel Synchronous Communications Controller
The CX28500 is an advanced Multichannel Synchronous
Communications Controller. It formats and deformats up to 1024 High-
level Data Link Control (HDLC) channels in a CMOS integrated circuit.
CX28500 operates at Layer 2 of the Open Systems Interconnection (OSI)
protocol reference model. It provides a comprehensive, high-density
solution for processing of HDLC channels for internetworking applications
such as Frame Relay, Integrated Services Digital Network (ISDN), D-
channel signaling, X.25, Signaling System 7 (SS7), Data Exchange
Interface (DXI), Inter System Link Protocol (ISLP), and LAN/WAN data
transport. Under minimal Host supervision, CX28500 manages table-like
data structures of channel data buffers in Host memory by performing
Direct Memory Access (DMA) of up to 1024 channels.
CX28500 interfaces to 32 independent serial data streams, such as T1/E1
signals. It then transfers data across the popular 32-bit or 64-bit Peripheral
Component Interface (PCI) bus to system memory at a rate up to 66 MHz.
The CX28500 has an aggregate data throughput of 390 Mbps. Each serial
interface can be operated up to 13.0 MHz. Six Serial Interfaces can be
operated at rates up to 52 MHz. Logical channels can be mapped as any
combination of Digital Signal Level 0 (DS0) time slots to support ISDN
hyperchannels (N x 64 Kbps). Additionally, logical channels can operate in
subchanneling mode (N x 8 Kbps) by mapping a combination of DS0 time
slots and/or the individual bits of a DS0 time slot (8 bits). For example, a
56 Kbps channel can be achieved by mapping 7 bits out of 8 possible bits
in a time slot (7 x 8 Kbps = 56 Kbps). CX28500 also includes a 32-bit
expansion port for bridging the PCI bus to local microprocessors or
peripherals. A Joint Test Action Group (JTAG) port enables boundary-
scan testing to replace bed-of-nails board testing.
Functional Block Diagram
28500-DSH-002-C
Configuration
Configuration
(Function 0)
Registers
Interface
Interface
Device
EXP BUS
Space
HOST
(PCI)
PCI
PCI
Local BUS
RxDMA
TxDMA
and
JTAG
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Processor
Processor
Rx Line
Tx Line
RSLP
TSLP
Access
Interface
Test
Serial
(SIU)
Unit
0
31
Highway
TSBUS
PCM
or
®
Distinguishing Features
1024-channel HDLC controller
OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
32 Independent serial interfaces, which
support:
Configurable logical channels
Per-channel protocol mode selection
Hardware Flow Control (CTS)
Selectable Endian configuration on data
Per-channel DMA buffer management
Per-channel message length check
Direct PCI bus interface
Host back-to-back transaction over the PCI
HSSI interfaces (52 Mbps)
Local expansion bus interface (EBUS)
TSBUS
Support of 64-bit ECC host memory
Low power, 3.3 V CMOS operation
JTAG boundary scan access port
35 mm x 35 mm 580-pin BGA
Available in Green (RoHS compliant) as well
as standard version
X.25 (LAPB)
Frame relay (LAPF/ANSI T1.618)
ISDN D-channel (LAPD/Q.921)
ISLP support
Mixed Data Rates (combination of T1/E1/
T3/E3, etc.) as long as they do not exceed
each port’s respective bandwidth
limitation and the overall device
bandwidth of 390 Mbps per direction
32 T1/E1 data streams
6 HSSI interfaces (52 Mbps)
DC to 13.0 Mbps serial interfaces
32 x 8.192 MHz TDM busses
Standard DS0 (56, 64 Kbps)
Subchanneling (N x 8 Kbps)
Hyperchannel (N x 64 Kbps)
Unchannelized mode
Non-FCS mode
16-bit FCS mode
32-bit FCS mode
Transparent mode (unformatted data)
Table-like data structures
Variable size transmit/receive FIFO
Select no length checking
Select from three 14-bit registers to
compare message length
32/64-bit, 33/66 MHz operation
Bus master and slave operation
PCI Version 2.1
32-bit multiplexed address/data bus
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